library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

use work.bpac.all;
ENTITY peakdetect IS
PORT(
 data	: IN	STD_LOGIC_VECTOR(5 downto 0);
 clk,set	: IN	STD_LOGIC;
 dataout	: OUT	STD_LOGIC_VECTOR(5 downto 0));
END peakdetect ;
ARCHITECTURE rtl OF peakdetect  IS
	SIGNAL peak : STD_LOGIC_VECTOR(5 downto 0);
	BEGIN
dataout<=peak;
process(clk)
begin
  if(clk'event and clk='1')then
  if(set='1')then
   peak<=data;
   else
    peak<=max (data,peak);
     end if;
      end if;
    end process;
 end rtl;