?? nand_2.vhd
字號:
--與非門多結構體的配置
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--*******************************
ENTITY nand_2 IS
PORT(
a,b: IN bit;
y: OUT bit);
END nand_2;
--*******************************
ARCHITECTURE rtl OF nand_2 IS
begin
y<=not(a and b);
end rtl;
--**********************************
ARCHITECTURE struct OF nand_2 IS
component inv_comp
port(a:in bit;
c:out bit);
end component;
component and2_comp
port(a,b:in bit;
c:out bit);
end component;
signal out1:bit;
begin
u1:and2_comp port map(a,b,out1);
u2:inv_comp port map(out1,y);
END struct;
--***********************************
ARCHITECTURE behav OF nand_2 IS
begin
process(a,b)
variable tmp: bit_vector(1 downto 0);
begin
tmp:=a&b;
case tmp is
when"00"=>y<='1';
when"01"=>y<='1';
when"10"=>y<='1';
when"11"=>y<='0';
end case;
end process;
end behav;
--*************************************
configuration nand2_con of nand_2 is
for rtl
end for;
end nand2_con;
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