library ieee;
use ieee.std_logic_1164.all;      --定義庫                            
--********************
entity dfff1 is 
port(d,clk : in std_logic;
          q: out std_logic);
end;
--*************************
architecture setup_time of dfff1 is
begin
process(clk)
begin
   if (clk='1') and (clk'event) then
   q<=d;
   assert(d'last_event>5 ns)
   report"setup violation"
   severity error;
 end if;
end process;
end setup_time;