LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
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ENTITY cntm60v IS
		PORT(en: IN std_logic;
             clr:in std_logic;
             clk:in  std_logic;
              cont:out  std_logic;
              qh:buffer  std_logic_vector(3 downto 0);
				ql: buffer  std_logic_vector(3 downto 0));
END ;
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ARCHITECTURE beh OF cntm60v IS
 BEGIN 
  cont<='1'when (qh="0101"and ql="1001"and en='1')else '0';
  PROCESS(CLK,clr)
     BEGIN
       IF(clr='0')THEN
          qh<="0000";
          ql<="0000";
        elsif (clk'event and clk='1')then
       IF(en='1')THEN
          if(ql=9)then
               ql<="0000";
              if(qh=5)then
               qh<="0000";
                else
                 qh<=qh+1;
               end if;
              else
              ql<=ql+1;
              end if;
           end if;
         end if;
       end process;
  end beh;