LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY bcdadd4 IS
	PORT (op1, op2	: in std_logic_vector(3 downto 0);
		   result	: out std_logic_vector(4 downto 0)
        );
END bcdadd4;

ARCHITECTURE behavior OF bcdadd4 IS
    signal   binadd    :std_logic_vector(4 downto 0);
BEGIN
  binadd<=('0' & op1) +('0' & op2);
  process(binadd)
   begin
     if binadd>9 then   
        result <= binadd+6;
       else
         result <= binadd;
     end if;   
  end process;      
END behavior;