-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux3v is
 port(a,b,c : in std_logic_vector(3 downto 0);
       sel : in std_logic_vector(1 downto 0);
       q: OUT std_logic_vector(3 downto 0));
end;
architecture abc of mux3v is
begin 
  process(a,b,c,sel)
   begin
    case sel is
    when "00"=>q<=a;
    when "01"=>q<=b;
    when "10"=>q<=c;
    when others=>null;
    end case;
    end process;
    end abc;