?? gat.vhd
字號:
library ieee;
use ieee.std_logic_1164.all; --庫定義
--*************************--
ENTITY gat IS
generic(l_time:time;s_time:time);
PORT(
b1,b2,b3 : inout bit);
END gat ; --端口定義
--************************************
ARCHITECTURE func OF gat IS
BEGIN
signal a1: bit;
begin
blk1:block
generic(gb1,gb2:time);
generic map(gb1=>l_time,gb2=>s_time);
PORT (gb1:in bit;gb2:inout bit);
PORT map(gb1=>b1, gb2=>a1);
constant delay:time:=1 ms;
signal s1:bit;
begin
s1<=gb1 after delay;
gb2<=s1 after gb1,b1 after gb2;
end block blk1;
end func;
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