LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity nd41 is
PORT(
         A1,B1,C1,D1: IN STD_LOGIC;
          z1:OUT STD_LOGIC);
   END ND41;
ARCHITECTURE AB OF ND41 IS
COMPONENT ND2
      PORT(
         A,B : IN STD_LOGIC;
          C  :OUT STD_LOGIC
      );
END COMPONENT;
SIGNAL  X,Y:STD_LOGIC;
  BEGIN
     U1:ND2 PORT MAP(B1,A1,x);
     U2:ND2 PORT MAP(A=>C1,C=>Y,B=>D1);
     U3:ND2 PORT MAP(X,Y,C=>Z1);
END ARCHITECTURE AB;