?? dev164.acf

?? vhdl基本門電路
?? ACF
?? 第 1 頁 / 共 2 頁
字號:
上一頁 12
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = ON;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = ON;
	SUBFACTOR_EXTRACTION = ON;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = 2;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = 32;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = ON;
	SUBFACTOR_EXTRACTION = ON;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = ON;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = ON;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = ON;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
	CASCADE_CHAIN = AUTO;
	CASCADE_CHAIN_LENGTH = 2;
	CARRY_CHAIN = AUTO;
	CARRY_CHAIN_LENGTH = 32;
	MINIMIZATION = FULL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = ON;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = ON;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = PARTIAL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	DECOMPOSE_GATES = OFF;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = PARTIAL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	DECOMPOSE_GATES = OFF;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
	CASCADE_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CARRY_CHAIN_LENGTH = -1;
	MINIMIZATION = PARTIAL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = ON;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	FAST_IO = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	DECOMPOSE_GATES = ON;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
	CASCADE_CHAIN = MANUAL;
	CASCADE_CHAIN_LENGTH = 2;
	CARRY_CHAIN = MANUAL;
	CARRY_CHAIN_LENGTH = 32;
	MINIMIZATION = PARTIAL;
	SLOW_SLEW_RATE = OFF;
	XOR_SYNTHESIS = OFF;
	TURBO_BIT = OFF;
	PARALLEL_EXPANDERS = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	SOFT_BUFFER_INSERTION = ON;
	DECOMPOSE_GATES = OFF;
	REDUCE_LOGIC = OFF;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	REFACTORIZATION = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	REGISTER_OPTIMIZATION = OFF;
END;
上一頁 12
?? 文件大小 1796 K
?? 上傳用戶 5201314
?? 所屬分類 VHDL/FPGA/Verilog
??? 相關標簽

#vhdl #門電路
?? 快捷鍵說明

復制代碼 Ctrl + C
搜索代碼 Ctrl + F
全屏模式 F11
切換主題 Ctrl + Shift + D
顯示快捷鍵 ?
增大字號 Ctrl + =
減小字號 Ctrl + -
亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频

?? dev164.acf

?? 快捷鍵說明
