LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY ex72 IS

	PORT
	(
		in1: STD_LOGIC_vector;
		pout		: OUT 	STD_LOGIC_vector
	);
	
END ex72;

ARCHITECTURE a OF ex72 IS
BEGIN

	PROCESS (in1)
	BEGIN	
       pout<=in1        after   3 ns;		
	END PROCESS;
END a;