?? dev164.vhd
字號:
-- 74164 vhdl描述
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY dev164 IS
PORT(a, b, nclr, clock : IN BIT;
q : BUFFER BIT_VECTOR(0 TO 7));
END dev164;
ARCHITECTURE version1 OF dev164 IS
BEGIN
PROCESS(a,b,nclr,clock)
BEGIN
IF nclr = '0' THEN
q <= "00000000";
ELSE
IF clock'EVENT AND clock = '1'
THEN
-- FOR i IN 1 to 7 LOOP 使用這結構編譯有錯
-- if i=0 then q(i)<=(a AND b);
-- else q(i) <= q(i-1);
-- END LOOP;
q(0) <= (a AND b);
FOR i IN 1 to 7 LOOP
q(i) <= q(i-1);
END LOOP;
END IF;
END IF;
END PROCESS;
END version1;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -