lIbrary ieee;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY LATCH IS
 PORT(
     D,ENA: IN STD_LOGIC;
        Q :OUT STD_LOGIC
      );
END;
ARCHITECTURE A OF LATCH IS
  SIGNAL TEMP:STD_LOGIC;
  BEGIN
    PROCESS(D,ENA)
     BEGIN
       IF ENA='1' THEN 
        TEMP<=D;
       END IF;
    Q<=TEMP;
   END PROCESS;
END A;