library ieee;
use ieee.std_logic_1164.all;
entity test25 is 
port(sel :in bit_vector(1 downto 0);
     a:in bit_vector(3 downto 0);
     b:in bit_vector(3 downto 0);
     c:in bit_vector(3 downto 0);
     q: out bit_vector(3 downto 0)
);
end;
architecture behav of test25 is
begin
process(sel,a,b,c)
begin
case sel is
   when "00"=>q<=a;
   when "01"=>q<=b;
   when "10"=>q<=c;
   when others=>null;
end case;
end process;
end behav;