--dff1---component----
library ieee;
use ieee.std_logic_1164.all;                          
--********************---
entity dff1 is 
port(d,clk : in std_logic;
          q: out std_logic);
end;
--*************************
architecture setup_time of dff1 is
begin
process(clk)
begin
   if (clk='1') and (clk'event) then
   q<=d;
    end if;
end process;
end setup_time;