?? ex11.rpt
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Project Information d:\vhdl_ex\ex11.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 10/13/2003 19:38:22
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
EX11
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
ex11 EPM7032LC44-6 5 7 0 24 1 75 %
User Pins: 5 7 0
Device-Specific Information: d:\vhdl_ex\ex11.rpt
ex11
***** Logic for device 'ex11' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
R R
E E
S S
E E
R R
V G G G G G V V
D D C N N N N N E E
1 0 G C D D D D D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
D2 | 7 39 | RESERVED
D3 | 8 38 | RESERVED
Q0 | 9 37 | RESERVED
GND | 10 36 | RESERVED
Q1 | 11 35 | VCC
RESERVED | 12 EPM7032LC44-6 34 | RESERVED
Q4 | 13 33 | RESERVED
Q5 | 14 32 | RESERVED
VCC | 15 31 | Q2
RESERVED | 16 30 | GND
RESERVED | 17 29 | Q3
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R Q
E E E E N C E E E E 6
S S S S D C S S S S
E E E E E E E E
R R R R R R R R
V V V V V V V V
E E E E E E E E
D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\vhdl_ex\ex11.rpt
ex11
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 8/16( 50%) 9/16( 56%) 0/16( 0%) 9/36( 25%)
B: LC17 - LC32 16/16(100%) 3/16( 18%) 5/16( 31%) 14/36( 38%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 12/32 ( 37%)
Total logic cells used: 24/32 ( 75%)
Total shareable expanders used: 1/32 ( 3%)
Total Turbo logic cells used: 24/32 ( 75%)
Total shareable expanders not available (n/a): 4/32 ( 12%)
Average fan-in: 4.20
Total fan-in: 101
Total input pins required: 5
Total output pins required: 7
Total bidirectional pins required: 0
Total logic cells required: 24
Total flipflops required: 0
Total product terms required: 77
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 1
Synthesized logic cells: 17/ 32 ( 53%)
Device-Specific Information: d:\vhdl_ex\ex11.rpt
ex11
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
5 (2) (A) INPUT 0 0 0 0 0 1 13 D0
6 (3) (A) INPUT 0 0 0 0 0 1 13 D1
7 (4) (A) INPUT 0 0 0 0 0 1 13 D2
8 (5) (A) INPUT 0 0 0 0 0 1 13 D3
4 (1) (A) INPUT 0 0 0 0 0 7 8 G
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl_ex\ex11.rpt
ex11
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
9 6 A OUTPUT t 0 0 0 1 2 0 0 Q0
11 7 A OUTPUT t 0 0 0 1 2 0 0 Q1
31 26 B OUTPUT t 0 0 0 1 2 0 0 Q2
29 27 B OUTPUT t 0 0 0 1 2 0 0 Q3
13 9 A OUTPUT t 0 0 0 1 2 0 0 Q4
14 10 A OUTPUT t 0 0 0 1 2 0 0 Q5
28 28 B OUTPUT t 1 1 0 5 2 0 0 Q6
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl_ex\ex11.rpt
ex11
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(24) 32 B SOFT s t 0 0 0 4 0 1 0 ~534~1
(25) 31 B SOFT s t 1 1 0 4 0 1 1 ~594~1
(36) 22 B SOFT s t 1 1 0 4 0 1 1 ~642~1
(37) 21 B SOFT s t 1 1 0 4 0 1 0 ~690~1
(38) 20 B SOFT s t 1 1 0 4 0 1 0 ~738~1
(39) 19 B SOFT s t 1 1 0 4 0 1 1 ~786~1
(40) 18 B SOFT s t 1 1 0 4 0 1 1 ~834~1
(41) 17 B LCELL s t 0 0 0 4 1 0 1 ~875~1~2
(34) 23 B LCELL s t 1 0 1 5 2 1 2 ~875~1
(7) 4 A LCELL s t 0 0 0 1 2 1 1 ~881~1
(8) 5 A LCELL s t 0 0 0 1 2 1 1 ~887~1
(33) 24 B LCELL s t 2 1 1 5 1 0 1 ~893~1~2
(32) 25 B LCELL s t 2 1 1 5 1 1 1 ~893~1
(27) 29 B LCELL s t 1 1 0 4 1 0 1 ~899~1~2
(26) 30 B LCELL s t 2 1 1 5 2 1 2 ~899~1
(12) 8 A LCELL s t 0 0 0 1 2 1 1 ~905~1
(17) 12 A LCELL s t 0 0 0 1 2 1 1 ~911~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl_ex\ex11.rpt
ex11
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------- LC6 Q0
| +------------- LC7 Q1
| | +----------- LC9 Q4
| | | +--------- LC10 Q5
| | | | +------- LC4 ~881~1
| | | | | +----- LC5 ~887~1
| | | | | | +--- LC8 ~905~1
| | | | | | | +- LC12 ~911~1
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'A'
LC | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC4 -> - - - * * - - - | * - | <-- ~881~1
LC5 -> - - * - - * - - | * - | <-- ~887~1
LC8 -> - * - - - - * - | * - | <-- ~905~1
LC12 -> * - - - - - - * | * - | <-- ~911~1
Pin
4 -> * * * * * * * * | * * | <-- G
LC31 -> - - - * * - - - | * - | <-- ~594~1
LC22 -> - - * - - * - - | * - | <-- ~642~1
LC19 -> - * - - - - * - | * - | <-- ~786~1
LC18 -> * - - - - - - * | * - | <-- ~834~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl_ex\ex11.rpt
ex11
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC26 Q2
| +----------------------------- LC27 Q3
| | +--------------------------- LC28 Q6
| | | +------------------------- LC32 ~534~1
| | | | +----------------------- LC31 ~594~1
| | | | | +--------------------- LC22 ~642~1
| | | | | | +------------------- LC21 ~690~1
| | | | | | | +----------------- LC20 ~738~1
| | | | | | | | +--------------- LC19 ~786~1
| | | | | | | | | +------------- LC18 ~834~1
| | | | | | | | | | +----------- LC17 ~875~1~2
| | | | | | | | | | | +--------- LC23 ~875~1
| | | | | | | | | | | | +------- LC24 ~893~1~2
| | | | | | | | | | | | | +----- LC25 ~893~1
| | | | | | | | | | | | | | +--- LC29 ~899~1~2
| | | | | | | | | | | | | | | +- LC30 ~899~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC32 -> - - * - - - - - - - - - - - - - | - * | <-- ~534~1
LC21 -> - * - - - - - - - - - - - - - - | - * | <-- ~690~1
LC20 -> * - - - - - - - - - - - - - - - | - * | <-- ~738~1
LC17 -> - - - - - - - - - - - * - - - - | - * | <-- ~875~1~2
LC23 -> - - * - - - - - - - * * - - - - | - * | <-- ~875~1
LC24 -> - - - - - - - - - - - - - * - - | - * | <-- ~893~1~2
LC25 -> - * - - - - - - - - - - * - - - | - * | <-- ~893~1
LC29 -> - - - - - - - - - - - - - - - * | - * | <-- ~899~1~2
LC30 -> * - - - - - - - - - - - - - * * | - * | <-- ~899~1
Pin
5 -> - - * * * * * * * * * * * * * * | - * | <-- D0
6 -> - - * * * * * * * * * * * * * * | - * | <-- D1
7 -> - - * * * * * * * * * * * * * * | - * | <-- D2
8 -> - - * * * * * * * * * * * * * * | - * | <-- D3
4 -> * * * - - - - - - - - * * * - * | * * | <-- G
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl_ex\ex11.rpt
ex11
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