?? ex11.rpt
字號:
** EQUATIONS **
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
G : INPUT;
-- Node name is 'Q0'
-- Equation name is 'Q0', location is LC006, type is output.
Q0 = LCELL( _EQ001 $ GND);
_EQ001 = G & _LC018
# !G & _LC012;
-- Node name is 'Q1'
-- Equation name is 'Q1', location is LC007, type is output.
Q1 = LCELL( _EQ002 $ GND);
_EQ002 = G & _LC019
# !G & _LC008;
-- Node name is 'Q2'
-- Equation name is 'Q2', location is LC026, type is output.
Q2 = LCELL( _EQ003 $ GND);
_EQ003 = G & _LC020
# !G & _LC030;
-- Node name is 'Q3'
-- Equation name is 'Q3', location is LC027, type is output.
Q3 = LCELL( _EQ004 $ GND);
_EQ004 = G & _LC021
# !G & _LC025;
-- Node name is 'Q4'
-- Equation name is 'Q4', location is LC009, type is output.
Q4 = LCELL( _EQ005 $ GND);
_EQ005 = G & _LC022
# !G & _LC005;
-- Node name is 'Q5'
-- Equation name is 'Q5', location is LC010, type is output.
Q5 = LCELL( _EQ006 $ GND);
_EQ006 = G & _LC031
# !G & _LC004;
-- Node name is 'Q6'
-- Equation name is 'Q6', location is LC028, type is output.
Q6 = LCELL( _EQ007 $ GND);
_EQ007 = G & _LC032 & _X001
# !G & _LC023;
_X001 = EXP(!D0 & !D1 & !D2 & !D3);
-- Node name is '~534~1'
-- Equation name is '~534~1', location is LC032, type is buried.
-- synthesized logic cell
_LC032 = LCELL( _EQ008 $ !D3);
_EQ008 = D0 & D1 & D2 & !D3
# !D1 & !D2 & !D3;
-- Node name is '~594~1'
-- Equation name is '~594~1', location is LC031, type is buried.
-- synthesized logic cell
_LC031 = LCELL( _EQ009 $ VCC);
_EQ009 = D0 & D1 & !D3 & _X001
# D0 & !D2 & !D3 & _X001
# D1 & !D2 & !D3 & _X001
# !D1 & !D2 & D3 & _X001;
_X001 = EXP(!D0 & !D1 & !D2 & !D3);
-- Node name is '~642~1'
-- Equation name is '~642~1', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ010 $ VCC);
_EQ010 = !D1 & D2 & !D3 & _X001
# !D1 & !D2 & D3 & _X001
# D0 & !D3 & _X001;
_X001 = EXP(!D0 & !D1 & !D2 & !D3);
-- Node name is '~690~1'
-- Equation name is '~690~1', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ011 $ _EQ012);
_EQ011 = D0 & !D1 & D2 & !D3 & _X001
# D1 & !D2 & !D3 & _X001
# !D0 & D1 & !D3 & _X001;
_X001 = EXP(!D0 & !D1 & !D2 & !D3);
_EQ012 = !D0 & !D1 & !D2 & !D3;
-- Node name is '~738~1'
-- Equation name is '~738~1', location is LC020, type is buried.
-- synthesized logic cell
_LC020 = LCELL( _EQ013 $ VCC);
_EQ013 = D0 & D1 & D2 & _X001
# !D0 & !D2 & _X001
# D3 & _X001;
_X001 = EXP(!D0 & !D1 & !D2 & !D3);
-- Node name is '~786~1'
-- Equation name is '~786~1', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ014 $ _EQ015);
_EQ014 = !D0 & !D1 & D2 & !D3 & _X001
# D1 & !D2 & !D3 & _X001
# D0 & !D2 & !D3 & _X001;
_X001 = EXP(!D0 & !D1 & !D2 & !D3);
_EQ015 = !D0 & !D1 & !D2 & !D3;
-- Node name is '~834~1'
-- Equation name is '~834~1', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ016 $ _EQ017);
_EQ016 = D0 & !D1 & D2 & !D3 & _X001
# D0 & D1 & !D2 & !D3 & _X001;
_X001 = EXP(!D0 & !D1 & !D2 & !D3);
_EQ017 = !D0 & !D1 & !D2 & !D3;
-- Node name is '~875~1~2'
-- Equation name is '~875~1~2', location is LC017, type is buried.
-- synthesized logic cell
_LC017 = LCELL( _EQ018 $ GND);
_EQ018 = D0 & D1 & D2 & !_LC023
# !D1 & !D2 & !_LC023
# D3 & !_LC023;
-- Node name is '~875~1'
-- Equation name is '~875~1', location is LC023, type is buried.
-- synthesized logic cell
_LC023 = LCELL( _EQ019 $ VCC);
_EQ019 = D0 & D1 & D2 & G
# !D1 & !D2 & G
# D3 & G
# !G & !_LC023
# _LC017;
-- Node name is '~881~1'
-- Equation name is '~881~1', location is LC004, type is buried.
-- synthesized logic cell
_LC004 = LCELL( _EQ020 $ GND);
_EQ020 = G & _LC031
# !G & _LC004
# _LC004 & _LC031;
-- Node name is '~887~1'
-- Equation name is '~887~1', location is LC005, type is buried.
-- synthesized logic cell
_LC005 = LCELL( _EQ021 $ GND);
_EQ021 = G & _LC022
# !G & _LC005
# _LC005 & _LC022;
-- Node name is '~893~1~2'
-- Equation name is '~893~1~2', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ022 $ GND);
_EQ022 = D0 & D1 & D2 & !_LC025 & _X001
# !D0 & !D1 & !_LC025 & _X001
# !D1 & !D2 & !_LC025 & _X001
# D3 & !_LC025 & _X001
# !G & !_LC025;
_X001 = EXP(!D0 & !D1 & !D2 & !D3);
-- Node name is '~893~1'
-- Equation name is '~893~1', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ023 $ VCC);
_EQ023 = D0 & D1 & D2 & G & _X001
# !D0 & !D1 & G & _X001
# !D1 & !D2 & G & _X001
# D3 & G & _X001
# _LC024;
_X001 = EXP(!D0 & !D1 & !D2 & !D3);
-- Node name is '~899~1~2'
-- Equation name is '~899~1~2', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ024 $ GND);
_EQ024 = D0 & D1 & D2 & !_LC030 & _X001
# !D0 & !D2 & !_LC030 & _X001
# D3 & !_LC030 & _X001;
_X001 = EXP(!D0 & !D1 & !D2 & !D3);
-- Node name is '~899~1'
-- Equation name is '~899~1', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ025 $ VCC);
_EQ025 = D0 & D1 & D2 & G & _X001
# !D0 & !D2 & G & _X001
# D3 & G & _X001
# !G & !_LC030
# _LC029;
_X001 = EXP(!D0 & !D1 & !D2 & !D3);
-- Node name is '~905~1'
-- Equation name is '~905~1', location is LC008, type is buried.
-- synthesized logic cell
_LC008 = LCELL( _EQ026 $ GND);
_EQ026 = G & _LC019
# !G & _LC008
# _LC008 & _LC019;
-- Node name is '~911~1'
-- Equation name is '~911~1', location is LC012, type is buried.
-- synthesized logic cell
_LC012 = LCELL( _EQ027 $ GND);
_EQ027 = G & _LC018
# !G & _LC012
# _LC012 & _LC018;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl_ex\ex11.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
ADT PALACE Compilation = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,275K
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