library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity gray is
port(G:in std_logic_vector(3 downto 0);
     en:in std_logic;
     B:out std_logic_vector(3 downto 0));
end GRAY;

architecture bin of gray is
begin
 B(3)<=G(3) AND EN;
 B(2)<=(((not G(3)) and G(2))or(G(3)and(not G(2)))) AND EN;
 B(1)<=(((not G(3))and(NOT G(2))AND(G(1)))or
       ((NOT G(3))and(G(2))AND(NOT G(1)))or
       ((G(3))and(G(2))AND(G(1)))or
       ((G(3))and(NOT G(2))AND(NOT G(1))))AND EN; 
 B(0)<=(((NOT G(3))AND(NOT G(2))AND(NOT G(1))AND(G(0)))or
       ((NOT G(3))AND(NOT G(2))AND(G(1))AND(NOT G(0)))or
       ((NOT G(3))AND(G(2))AND(G(1))AND(G(0)))or
       ((NOT G(3))AND(G(2))AND(NOT G(1))AND(NOT G(0)))or    
       ( G(3) AND (NOT G(2)) AND G(1) AND G(0))or
       ( G(3) AND G(2) AND(NOT G(1))AND G(0))or
       ( G(3) AND G(2) AND G(1) AND (NOT G(0)))or
       ( G(3) AND (NOT G(2)) AND (NOT G(1)) AND (NOT G(0))))AND EN;
end bin;