library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--*************************
entity count60s is
port(
    clk:in std_logic;
    resets:in std_logic;
    rcos:out std_logic;
   qh,ql:buffer std_logic_vector(3 downto 0)
   );
end count60s;
--******************************
architecture datablow of count60s is
begin
process(clk,resets)
begin
wait until(clk'event and clk='1');
if resets='1'or (qh="0101"and ql="1001")then
qh<="0000";
ql<="0000";
rcos<='1';
else
if ql="1001"then
   ql<="0000";
qh<=qh+1;
if qh="0101"then
qh<="0000";
else
qh<=qh+1;
end if;
else
ql<=ql+1;
end if;
rcos<='0';
end if;
end process;
end datablow;