?? ex82.vhd
字號:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY EX82 IS
GENERIC(SIZE:INTEGER :=8);
PORT(
D1,CP : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR((SIZE-1) DOWNTO 0));
END EX82;
ARCHITECTURE A OF EX82 IS
COMPONENT DFF
PORT(
D,CLK : IN STD_LOGIC;
Q : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL TEMP :STD_LOGIC_VECTOR(SIZE DOWNTO 0);
BEGIN
TEMP(0)<=D1;
LABEL1:FOR I IN 0 TO 3 GENERATE
DFFX:DFF PORT MAP (TEMP(I),CP,TEMP(I+1));
END GENERATE LABEL1;
Q<=TEMP(SIZE DOWNTO 1);
END A;
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