LIBRARY IEEE;
LIBRARY ALTERA;
USE ALTERA.MAXPLUS2.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY USEA74 IS
 PORT(
       OEN,G:IN STD_LOGIC;
           D:IN STD_LOGIC_VECTOR(8 DOWNTO 1);
           Q:OUT STD_LOGIC_VECTOR(8 DOWNTO 1)
      );
END;
ARCHITECTURE A OF USEA74 IS
  BEGIN
      AAA:a_74373 PORT MAP(OEN,G,D,Q);
END A;