40     18    B     OUTPUT      t        0      0   0    1    0    0    0  A1
  37     21    B     OUTPUT      t        0      0   0    1    0    0    0  A2
  33     24    B     OUTPUT      t        0      0   0    1    0    0    0  A3
  31     26    B     OUTPUT      t        0      0   0    1    0    0    0  A4
  34     23    B     OUTPUT      t        0      0   0    1    0    0    0  A5
  36     22    B     OUTPUT      t        0      0   0    1    0    0    0  A6
  39     19    B     OUTPUT      t        0      0   0    1    0    0    0  A7
  41     17    B     OUTPUT      t        0      0   0    1    0    0    0  A8


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               d:\vhdl_ex\ex09.rpt
ex09

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                         Logic cells placed in LAB 'B'
        +--------------- LC18 A1
        | +------------- LC21 A2
        | | +----------- LC24 A3
        | | | +--------- LC26 A4
        | | | | +------- LC23 A5
        | | | | | +----- LC22 A6
        | | | | | | +--- LC19 A7
        | | | | | | | +- LC17 A8
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'B':

Pin
4    -> * - - - - - - - | - * | <-- B1
5    -> - * - - - - - - | - * | <-- B2
6    -> - - * - - - - - | - * | <-- B3
8    -> - - - * - - - - | - * | <-- B4
9    -> - - - - * - - - | - * | <-- B5
11   -> - - - - - * - - | - * | <-- B6
12   -> - - - - - - * - | - * | <-- B7
14   -> - - - - - - - * | - * | <-- B8


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               d:\vhdl_ex\ex09.rpt
ex09

** EQUATIONS **

B1       : INPUT;
B2       : INPUT;
B3       : INPUT;
B4       : INPUT;
B5       : INPUT;
B6       : INPUT;
B7       : INPUT;
B8       : INPUT;

-- Node name is 'A1' 
-- Equation name is 'A1', location is LC018, type is output.
 A1      = LCELL( B1 $  GND);

-- Node name is 'A2' 
-- Equation name is 'A2', location is LC021, type is output.
 A2      = LCELL( B2 $  GND);

-- Node name is 'A3' 
-- Equation name is 'A3', location is LC024, type is output.
 A3      = LCELL( B3 $  GND);

-- Node name is 'A4' 
-- Equation name is 'A4', location is LC026, type is output.
 A4      = LCELL( B4 $  GND);

-- Node name is 'A5' 
-- Equation name is 'A5', location is LC023, type is output.
 A5      = LCELL( B5 $  GND);

-- Node name is 'A6' 
-- Equation name is 'A6', location is LC022, type is output.
 A6      = LCELL( B6 $  GND);

-- Node name is 'A7' 
-- Equation name is 'A7', location is LC019, type is output.
 A7      = LCELL( B7 $  GND);

-- Node name is 'A8' 
-- Equation name is 'A8', location is LC017, type is output.
 A8      = LCELL( B8 $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        d:\vhdl_ex\ex09.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off
ADT PALACE Compilation                    = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,807K