library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Carrier is
port(
	clk : in std_logic;
	C_Sin1 : out std_logic;
	C_Sin2 : out std_logic
	);
end Carrier;

architecture behave of Carrier is
signal cnt : std_logic_vector(7 downto 0);
begin
	process(clk)
	begin
		if rising_edge(clk) then
			cnt <= cnt + 1;
		end if;
	end process;
	C_Sin1 <= cnt(1);
	C_Sin2 <= cnt(4);
end behave;