?? fsk_demod.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FSK_Demod is
port(
clk : in std_logic;
FSK_in : in std_logic;
Demod : out std_logic
);
end FSK_Demod;
architecture behave of FSK_Demod is
signal cnt : std_logic_vector(7 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
cnt <= cnt + 1;
end if;
end process;
process(FSK_in)
variable m : integer range 0 to 6;
begin
if cnt > "11000000" then
if m >= 2 then
Demod <= '1';
else
Demod <= '0';
end if;
elsif rising_edge(FSK_in) then
m := m + 1;
end if;
end process;
end behave;
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