library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity FSK_Mod is
port(
	clk : in std_logic;
	C_in1 : in std_logic;
	C_in2 : in std_logic;
	Base_Sin : in std_logic;
	FSK_out : out std_logic
	);
end FSK_Mod;

architecture behave of FSK_Mod is
begin
	process(clk)
	begin
		if rising_edge(clk) then
			if Base_Sin = '1' then
				FSK_out <= C_in1;
			else
				FSK_out <= C_in2;
			end if;
		end if;
	end process;
end behave;