{ "Info" "ITDB_TSU_RESULT" "FSK_Mod:inst1\|FSK_out Base_Sin clk 4.336 ns register " "Info: tsu for register \"FSK_Mod:inst1\|FSK_out\" (data pin = \"Base_Sin\", clock pin = \"clk\") is 4.336 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.967 ns + Longest pin register " "Info: + Longest pin to register delay is 6.967 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns Base_Sin 1 PIN PIN_35 1 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_35; Fanout = 1; PIN Node = 'Base_Sin'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Base_Sin } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 224 -120 48 240 "Base_Sin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.668 ns) + CELL(0.206 ns) 6.859 ns FSK_Mod:inst1\|FSK_out~10 2 COMB LCCOMB_X1_Y5_N26 1 " "Info: 2: + IC(5.668 ns) + CELL(0.206 ns) = 6.859 ns; Loc. = LCCOMB_X1_Y5_N26; Fanout = 1; COMB Node = 'FSK_Mod:inst1\|FSK_out~10'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.874 ns" { Base_Sin FSK_Mod:inst1|FSK_out~10 } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.967 ns FSK_Mod:inst1\|FSK_out 3 REG LCFF_X1_Y5_N27 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.967 ns; Loc. = LCFF_X1_Y5_N27; Fanout = 2; REG Node = 'FSK_Mod:inst1\|FSK_out'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { FSK_Mod:inst1|FSK_out~10 FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.299 ns ( 18.65 % ) " "Info: Total cell delay = 1.299 ns ( 18.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.668 ns ( 81.35 % ) " "Info: Total interconnect delay = 5.668 ns ( 81.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.967 ns" { Base_Sin FSK_Mod:inst1|FSK_out~10 FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.967 ns" { Base_Sin {} Base_Sin~combout {} FSK_Mod:inst1|FSK_out~10 {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 5.668ns 0.000ns } { 0.000ns 0.985ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.591 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.591 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns clk 1 CLK PIN_32 9 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_32; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.666 ns) 2.591 ns FSK_Mod:inst1\|FSK_out 2 REG LCFF_X1_Y5_N27 2 " "Info: 2: + IC(0.940 ns) + CELL(0.666 ns) = 2.591 ns; Loc. = LCFF_X1_Y5_N27; Fanout = 2; REG Node = 'FSK_Mod:inst1\|FSK_out'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.606 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.651 ns ( 63.72 % ) " "Info: Total cell delay = 1.651 ns ( 63.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.940 ns ( 36.28 % ) " "Info: Total interconnect delay = 0.940 ns ( 36.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.591 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.591 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 0.940ns } { 0.000ns 0.985ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.967 ns" { Base_Sin FSK_Mod:inst1|FSK_out~10 FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.967 ns" { Base_Sin {} Base_Sin~combout {} FSK_Mod:inst1|FSK_out~10 {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 5.668ns 0.000ns } { 0.000ns 0.985ns 0.206ns 0.108ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.591 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.591 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 0.940ns } { 0.000ns 0.985ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Demod FSK_Demod:inst2\|Demod 9.923 ns register " "Info: tco from clock \"clk\" to destination pin \"Demod\" through register \"FSK_Demod:inst2\|Demod\" is 9.923 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.876 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.876 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns clk 1 CLK PIN_32 9 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_32; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.970 ns) 2.895 ns FSK_Demod:inst2\|cnt\[6\] 2 REG LCFF_X1_Y5_N19 3 " "Info: 2: + IC(0.940 ns) + CELL(0.970 ns) = 2.895 ns; Loc. = LCFF_X1_Y5_N19; Fanout = 3; REG Node = 'FSK_Demod:inst2\|cnt\[6\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.910 ns" { clk FSK_Demod:inst2|cnt[6] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.385 ns) + CELL(0.624 ns) 4.904 ns FSK_Demod:inst2\|LessThan0~109 3 COMB LCCOMB_X1_Y5_N2 4 " "Info: 3: + IC(1.385 ns) + CELL(0.624 ns) = 4.904 ns; Loc. = LCCOMB_X1_Y5_N2; Fanout = 4; COMB Node = 'FSK_Demod:inst2\|LessThan0~109'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.009 ns" { FSK_Demod:inst2|cnt[6] FSK_Demod:inst2|LessThan0~109 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.383 ns) + CELL(0.589 ns) 5.876 ns FSK_Demod:inst2\|Demod 4 REG LCCOMB_X1_Y5_N24 1 " "Info: 4: + IC(0.383 ns) + CELL(0.589 ns) = 5.876 ns; Loc. = LCCOMB_X1_Y5_N24; Fanout = 1; REG Node = 'FSK_Demod:inst2\|Demod'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.972 ns" { FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.168 ns ( 53.91 % ) " "Info: Total cell delay = 3.168 ns ( 53.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.708 ns ( 46.09 % ) " "Info: Total interconnect delay = 2.708 ns ( 46.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.876 ns" { clk FSK_Demod:inst2|cnt[6] FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.876 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[6] {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.000ns 0.940ns 1.385ns 0.383ns } { 0.000ns 0.985ns 0.970ns 0.624ns 0.589ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.047 ns + Longest register pin " "Info: + Longest register to pin delay is 4.047 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FSK_Demod:inst2\|Demod 1 REG LCCOMB_X1_Y5_N24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X1_Y5_N24; Fanout = 1; REG Node = 'FSK_Demod:inst2\|Demod'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|Demod } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.951 ns) + CELL(3.096 ns) 4.047 ns Demod 2 PIN PIN_31 0 " "Info: 2: + IC(0.951 ns) + CELL(3.096 ns) = 4.047 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'Demod'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.047 ns" { FSK_Demod:inst2|Demod Demod } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 96 912 1088 112 "Demod" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 76.50 % ) " "Info: Total cell delay = 3.096 ns ( 76.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.951 ns ( 23.50 % ) " "Info: Total interconnect delay = 0.951 ns ( 23.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.047 ns" { FSK_Demod:inst2|Demod Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.047 ns" { FSK_Demod:inst2|Demod {} Demod {} } { 0.000ns 0.951ns } { 0.000ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.876 ns" { clk FSK_Demod:inst2|cnt[6] FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.876 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[6] {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.000ns 0.940ns 1.385ns 0.383ns } { 0.000ns 0.985ns 0.970ns 0.624ns 0.589ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.047 ns" { FSK_Demod:inst2|Demod Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.047 ns" { FSK_Demod:inst2|Demod {} Demod {} } { 0.000ns 0.951ns } { 0.000ns 3.096ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "FSK_Mod:inst1\|FSK_out Base_Sin clk -4.070 ns register " "Info: th for register \"FSK_Mod:inst1\|FSK_out\" (data pin = \"Base_Sin\", clock pin = \"clk\") is -4.070 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.591 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.591 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns clk 1 CLK PIN_32 9 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_32; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.666 ns) 2.591 ns FSK_Mod:inst1\|FSK_out 2 REG LCFF_X1_Y5_N27 2 " "Info: 2: + IC(0.940 ns) + CELL(0.666 ns) = 2.591 ns; Loc. = LCFF_X1_Y5_N27; Fanout = 2; REG Node = 'FSK_Mod:inst1\|FSK_out'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.606 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.651 ns ( 63.72 % ) " "Info: Total cell delay = 1.651 ns ( 63.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.940 ns ( 36.28 % ) " "Info: Total interconnect delay = 0.940 ns ( 36.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.591 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.591 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 0.940ns } { 0.000ns 0.985ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.967 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.967 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns Base_Sin 1 PIN PIN_35 1 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_35; Fanout = 1; PIN Node = 'Base_Sin'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Base_Sin } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 224 -120 48 240 "Base_Sin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.668 ns) + CELL(0.206 ns) 6.859 ns FSK_Mod:inst1\|FSK_out~10 2 COMB LCCOMB_X1_Y5_N26 1 " "Info: 2: + IC(5.668 ns) + CELL(0.206 ns) = 6.859 ns; Loc. = LCCOMB_X1_Y5_N26; Fanout = 1; COMB Node = 'FSK_Mod:inst1\|FSK_out~10'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.874 ns" { Base_Sin FSK_Mod:inst1|FSK_out~10 } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.967 ns FSK_Mod:inst1\|FSK_out 3 REG LCFF_X1_Y5_N27 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.967 ns; Loc. = LCFF_X1_Y5_N27; Fanout = 2; REG Node = 'FSK_Mod:inst1\|FSK_out'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { FSK_Mod:inst1|FSK_out~10 FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.299 ns ( 18.65 % ) " "Info: Total cell delay = 1.299 ns ( 18.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.668 ns ( 81.35 % ) " "Info: Total interconnect delay = 5.668 ns ( 81.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.967 ns" { Base_Sin FSK_Mod:inst1|FSK_out~10 FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.967 ns" { Base_Sin {} Base_Sin~combout {} FSK_Mod:inst1|FSK_out~10 {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 5.668ns 0.000ns } { 0.000ns 0.985ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.591 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.591 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 0.940ns } { 0.000ns 0.985ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.967 ns" { Base_Sin FSK_Mod:inst1|FSK_out~10 FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.967 ns" { Base_Sin {} Base_Sin~combout {} FSK_Mod:inst1|FSK_out~10 {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 5.668ns 0.000ns } { 0.000ns 0.985ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}