{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 12 10:23:24 2008 " "Info: Processing started: Thu Jun 12 10:23:24 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off FSK -c FSK " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off FSK -c FSK" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "FSK EP2C5Q208C8 " "Info: Selected device EP2C5Q208C8 for design \"FSK\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "71 Top " "Info: Previous placement does not exist for 71 of 71 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208C8 " "Info: Device EP2C8Q208C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" {  } { { "d:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program files/altera/72/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" {  } { { "d:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program files/altera/72/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "4 5 " "Warning: No exact pin location assignment(s) for 4 pins of 5 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FSK_out " "Info: Pin FSK_out not assigned to an exact location on the device" {  } { { "d:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program files/altera/72/quartus/bin/pin_planner.ppl" { FSK_out } } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 256 680 856 272 "FSK_out" "" } } } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_out } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Demod " "Info: Pin Demod not assigned to an exact location on the device" {  } { { "d:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program files/altera/72/quartus/bin/pin_planner.ppl" { Demod } } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 96 912 1088 112 "Demod" "" } } } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Demod } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "Base_Sin " "Info: Pin Base_Sin not assigned to an exact location on the device" {  } { { "d:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program files/altera/72/quartus/bin/pin_planner.ppl" { Base_Sin } } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 224 -120 48 240 "Base_Sin" "" } } } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Base_Sin } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Base_Sin } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "d:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program files/altera/72/quartus/bin/pin_planner.ppl" { clk } } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 132 (CLK4, LVDSCLK2p, Input)) " "Info: Automatically promoted node clk (placed in PIN 132 (CLK4, LVDSCLK2p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G6 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FSK_Mod:inst1\|FSK_out " "Info: Destination node FSK_Mod:inst1\|FSK_out" {  } { { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Mod:inst1|FSK_out } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FSK_Demod:inst2\|cnt\[3\] " "Info: Destination node FSK_Demod:inst2\|cnt\[3\]" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[3] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FSK_Demod:inst2\|cnt\[1\] " "Info: Destination node FSK_Demod:inst2\|cnt\[1\]" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[1] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FSK_Demod:inst2\|cnt\[6\] " "Info: Destination node FSK_Demod:inst2\|cnt\[6\]" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[6] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[6] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FSK_Demod:inst2\|cnt\[7\] " "Info: Destination node FSK_Demod:inst2\|cnt\[7\]" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[7] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[7] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FSK_Demod:inst2\|cnt\[2\] " "Info: Destination node FSK_Demod:inst2\|cnt\[2\]" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[2] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[2] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FSK_Demod:inst2\|cnt\[4\] " "Info: Destination node FSK_Demod:inst2\|cnt\[4\]" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[4] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[4] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FSK_Demod:inst2\|cnt\[5\] " "Info: Destination node FSK_Demod:inst2\|cnt\[5\]" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[5] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FSK_Demod:inst2\|cnt\[0\] " "Info: Destination node FSK_Demod:inst2\|cnt\[0\]" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[0] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program files/altera/72/quartus/bin/pin_planner.ppl" { clk } } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}