?? fsk.tan.qmsg
字號(hào):
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register FSK_Demod:inst2\|m\[2\] register FSK_Demod:inst2\|Demod 134.48 MHz 7.436 ns Internal " "Info: Clock \"clk\" has Internal fmax of 134.48 MHz between source register \"FSK_Demod:inst2\|m\[2\]\" and destination register \"FSK_Demod:inst2\|Demod\" (period= 7.436 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.328 ns + Longest register register " "Info: + Longest register to register delay is 1.328 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FSK_Demod:inst2\|m\[2\] 1 REG LCFF_X27_Y5_N15 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X27_Y5_N15; Fanout = 2; REG Node = 'FSK_Demod:inst2\|m\[2\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|m[2] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.319 ns) 0.770 ns FSK_Demod:inst2\|LessThan1~24 2 COMB LCCOMB_X27_Y5_N22 1 " "Info: 2: + IC(0.451 ns) + CELL(0.319 ns) = 0.770 ns; Loc. = LCCOMB_X27_Y5_N22; Fanout = 1; COMB Node = 'FSK_Demod:inst2\|LessThan1~24'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.770 ns" { FSK_Demod:inst2|m[2] FSK_Demod:inst2|LessThan1~24 } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.352 ns) + CELL(0.206 ns) 1.328 ns FSK_Demod:inst2\|Demod 3 REG LCCOMB_X27_Y5_N16 1 " "Info: 3: + IC(0.352 ns) + CELL(0.206 ns) = 1.328 ns; Loc. = LCCOMB_X27_Y5_N16; Fanout = 1; REG Node = 'FSK_Demod:inst2\|Demod'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.558 ns" { FSK_Demod:inst2|LessThan1~24 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.525 ns ( 39.53 % ) " "Info: Total cell delay = 0.525 ns ( 39.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.803 ns ( 60.47 % ) " "Info: Total interconnect delay = 0.803 ns ( 60.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.328 ns" { FSK_Demod:inst2|m[2] FSK_Demod:inst2|LessThan1~24 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "1.328 ns" { FSK_Demod:inst2|m[2] {} FSK_Demod:inst2|LessThan1~24 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.451ns 0.352ns } { 0.000ns 0.319ns 0.206ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.716 ns - Smallest " "Info: - Smallest clock skew is -0.716 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.574 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.574 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns clk 1 CLK PIN_132 10 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_132; Fanout = 10; CLK Node = 'clk'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.286 ns) + CELL(0.970 ns) 3.406 ns FSK_Demod:inst2\|cnt\[0\] 2 REG LCFF_X26_Y5_N9 5 " "Info: 2: + IC(1.286 ns) + CELL(0.970 ns) = 3.406 ns; Loc. = LCFF_X26_Y5_N9; Fanout = 5; REG Node = 'FSK_Demod:inst2\|cnt\[0\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.256 ns" { clk FSK_Demod:inst2|cnt[0] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.206 ns) 4.685 ns FSK_Demod:inst2\|LessThan0~107 3 COMB LCCOMB_X27_Y5_N24 1 " "Info: 3: + IC(1.073 ns) + CELL(0.206 ns) = 4.685 ns; Loc. = LCCOMB_X27_Y5_N24; Fanout = 1; COMB Node = 'FSK_Demod:inst2\|LessThan0~107'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.279 ns" { FSK_Demod:inst2|cnt[0] FSK_Demod:inst2|LessThan0~107 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.655 ns) + CELL(0.206 ns) 5.546 ns FSK_Demod:inst2\|LessThan0~109 4 COMB LCCOMB_X27_Y5_N20 4 " "Info: 4: + IC(0.655 ns) + CELL(0.206 ns) = 5.546 ns; Loc. = LCCOMB_X27_Y5_N20; Fanout = 4; COMB Node = 'FSK_Demod:inst2\|LessThan0~109'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.861 ns" { FSK_Demod:inst2|LessThan0~107 FSK_Demod:inst2|LessThan0~109 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.615 ns) 6.574 ns FSK_Demod:inst2\|Demod 5 REG LCCOMB_X27_Y5_N16 1 " "Info: 5: + IC(0.413 ns) + CELL(0.615 ns) = 6.574 ns; Loc. = LCCOMB_X27_Y5_N16; Fanout = 1; REG Node = 'FSK_Demod:inst2\|Demod'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.028 ns" { FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.147 ns ( 47.87 % ) " "Info: Total cell delay = 3.147 ns ( 47.87 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.427 ns ( 52.13 % ) " "Info: Total interconnect delay = 3.427 ns ( 52.13 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.574 ns" { clk FSK_Demod:inst2|cnt[0] FSK_Demod:inst2|LessThan0~107 FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.574 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[0] {} FSK_Demod:inst2|LessThan0~107 {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.000ns 1.286ns 1.073ns 0.655ns 0.413ns } { 0.000ns 1.150ns 0.970ns 0.206ns 0.206ns 0.615ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.290 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.290 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns clk 1 CLK PIN_132 10 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_132; Fanout = 10; CLK Node = 'clk'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.952 ns) + CELL(0.970 ns) 3.072 ns FSK_Mod:inst1\|FSK_out 2 REG LCFF_X27_Y5_N19 2 " "Info: 2: + IC(0.952 ns) + CELL(0.970 ns) = 3.072 ns; Loc. = LCFF_X27_Y5_N19; Fanout = 2; REG Node = 'FSK_Mod:inst1\|FSK_out'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.922 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.713 ns) + CELL(0.000 ns) 5.785 ns FSK_Mod:inst1\|FSK_out~clkctrl 3 COMB CLKCTRL_G2 3 " "Info: 3: + IC(2.713 ns) + CELL(0.000 ns) = 5.785 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'FSK_Mod:inst1\|FSK_out~clkctrl'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 7.290 ns FSK_Demod:inst2\|m\[2\] 4 REG LCFF_X27_Y5_N15 2 " "Info: 4: + IC(0.839 ns) + CELL(0.666 ns) = 7.290 ns; Loc. = LCFF_X27_Y5_N15; Fanout = 2; REG Node = 'FSK_Demod:inst2\|m\[2\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[2] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.786 ns ( 38.22 % ) " "Info: Total cell delay = 2.786 ns ( 38.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.504 ns ( 61.78 % ) " "Info: Total interconnect delay = 4.504 ns ( 61.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.290 ns" { clk FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[2] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.290 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} FSK_Mod:inst1|FSK_out~clkctrl {} FSK_Demod:inst2|m[2] {} } { 0.000ns 0.000ns 0.952ns 2.713ns 0.839ns } { 0.000ns 1.150ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.574 ns" { clk FSK_Demod:inst2|cnt[0] FSK_Demod:inst2|LessThan0~107 FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.574 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[0] {} FSK_Demod:inst2|LessThan0~107 {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.000ns 1.286ns 1.073ns 0.655ns 0.413ns } { 0.000ns 1.150ns 0.970ns 0.206ns 0.206ns 0.615ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.290 ns" { clk FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[2] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.290 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} FSK_Mod:inst1|FSK_out~clkctrl {} FSK_Demod:inst2|m[2] {} } { 0.000ns 0.000ns 0.952ns 2.713ns 0.839ns } { 0.000ns 1.150ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.370 ns + " "Info: + Micro setup delay of destination is 1.370 ns" { } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.328 ns" { FSK_Demod:inst2|m[2] FSK_Demod:inst2|LessThan1~24 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "1.328 ns" { FSK_Demod:inst2|m[2] {} FSK_Demod:inst2|LessThan1~24 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.451ns 0.352ns } { 0.000ns 0.319ns 0.206ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.574 ns" { clk FSK_Demod:inst2|cnt[0] FSK_Demod:inst2|LessThan0~107 FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "6.574 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[0] {} FSK_Demod:inst2|LessThan0~107 {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.000ns 1.286ns 1.073ns 0.655ns 0.413ns } { 0.000ns 1.150ns 0.970ns 0.206ns 0.206ns 0.615ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.290 ns" { clk FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[2] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.290 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} FSK_Mod:inst1|FSK_out~clkctrl {} FSK_Demod:inst2|m[2] {} } { 0.000ns 0.000ns 0.952ns 2.713ns 0.839ns } { 0.000ns 1.150ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 24 " "Warning: Circuit may not operate. Detected 24 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "FSK_Demod:inst2\|cnt\[0\] FSK_Demod:inst2\|m\[1\] clk 876 ps " "Info: Found hold time violation between source pin or register \"FSK_Demod:inst2\|cnt\[0\]\" and destination pin or register \"FSK_Demod:inst2\|m\[1\]\" for clock \"clk\" (Hold time is 876 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.188 ns + Largest " "Info: + Largest clock skew is 4.188 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.290 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.290 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns clk 1 CLK PIN_132 10 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_132; Fanout = 10; CLK Node = 'clk'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.952 ns) + CELL(0.970 ns) 3.072 ns FSK_Mod:inst1\|FSK_out 2 REG LCFF_X27_Y5_N19 2 " "Info: 2: + IC(0.952 ns) + CELL(0.970 ns) = 3.072 ns; Loc. = LCFF_X27_Y5_N19; Fanout = 2; REG Node = 'FSK_Mod:inst1\|FSK_out'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.922 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.713 ns) + CELL(0.000 ns) 5.785 ns FSK_Mod:inst1\|FSK_out~clkctrl 3 COMB CLKCTRL_G2 3 " "Info: 3: + IC(2.713 ns) + CELL(0.000 ns) = 5.785 ns; Loc. = CLKCTRL_G2; Fanout = 3; COMB Node = 'FSK_Mod:inst1\|FSK_out~clkctrl'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.713 ns" { FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 7.290 ns FSK_Demod:inst2\|m\[1\] 4 REG LCFF_X27_Y5_N29 3 " "Info: 4: + IC(0.839 ns) + CELL(0.666 ns) = 7.290 ns; Loc. = LCFF_X27_Y5_N29; Fanout = 3; REG Node = 'FSK_Demod:inst2\|m\[1\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.786 ns ( 38.22 % ) " "Info: Total cell delay = 2.786 ns ( 38.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.504 ns ( 61.78 % ) " "Info: Total interconnect delay = 4.504 ns ( 61.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.290 ns" { clk FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.290 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} FSK_Mod:inst1|FSK_out~clkctrl {} FSK_Demod:inst2|m[1] {} } { 0.000ns 0.000ns 0.952ns 2.713ns 0.839ns } { 0.000ns 1.150ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.102 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns clk 1 CLK PIN_132 10 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_132; Fanout = 10; CLK Node = 'clk'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.286 ns) + CELL(0.666 ns) 3.102 ns FSK_Demod:inst2\|cnt\[0\] 2 REG LCFF_X26_Y5_N9 5 " "Info: 2: + IC(1.286 ns) + CELL(0.666 ns) = 3.102 ns; Loc. = LCFF_X26_Y5_N9; Fanout = 5; REG Node = 'FSK_Demod:inst2\|cnt\[0\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.952 ns" { clk FSK_Demod:inst2|cnt[0] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.816 ns ( 58.54 % ) " "Info: Total cell delay = 1.816 ns ( 58.54 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.286 ns ( 41.46 % ) " "Info: Total interconnect delay = 1.286 ns ( 41.46 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.102 ns" { clk FSK_Demod:inst2|cnt[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.102 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[0] {} } { 0.000ns 0.000ns 1.286ns } { 0.000ns 1.150ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.290 ns" { clk FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.290 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} FSK_Mod:inst1|FSK_out~clkctrl {} FSK_Demod:inst2|m[1] {} } { 0.000ns 0.000ns 0.952ns 2.713ns 0.839ns } { 0.000ns 1.150ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.102 ns" { clk FSK_Demod:inst2|cnt[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.102 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[0] {} } { 0.000ns 0.000ns 1.286ns } { 0.000ns 1.150ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" { } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.314 ns - Shortest register register " "Info: - Shortest register to register delay is 3.314 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FSK_Demod:inst2\|cnt\[0\] 1 REG LCFF_X26_Y5_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y5_N9; Fanout = 5; REG Node = 'FSK_Demod:inst2\|cnt\[0\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|cnt[0] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.206 ns) 1.279 ns FSK_Demod:inst2\|LessThan0~107 2 COMB LCCOMB_X27_Y5_N24 1 " "Info: 2: + IC(1.073 ns) + CELL(0.206 ns) = 1.279 ns; Loc. = LCCOMB_X27_Y5_N24; Fanout = 1; COMB Node = 'FSK_Demod:inst2\|LessThan0~107'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.279 ns" { FSK_Demod:inst2|cnt[0] FSK_Demod:inst2|LessThan0~107 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.655 ns) + CELL(0.206 ns) 2.140 ns FSK_Demod:inst2\|LessThan0~109 3 COMB LCCOMB_X27_Y5_N20 4 " "Info: 3: + IC(0.655 ns) + CELL(0.206 ns) = 2.140 ns; Loc. = LCCOMB_X27_Y5_N20; Fanout = 4; COMB Node = 'FSK_Demod:inst2\|LessThan0~109'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.861 ns" { FSK_Demod:inst2|LessThan0~107 FSK_Demod:inst2|LessThan0~109 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.651 ns) 3.206 ns FSK_Demod:inst2\|m\[1\]~205 4 COMB LCCOMB_X27_Y5_N28 1 " "Info: 4: + IC(0.415 ns) + CELL(0.651 ns) = 3.206 ns; Loc. = LCCOMB_X27_Y5_N28; Fanout = 1; COMB Node = 'FSK_Demod:inst2\|m\[1\]~205'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.066 ns" { FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|m[1]~205 } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.314 ns FSK_Demod:inst2\|m\[1\] 5 REG LCFF_X27_Y5_N29 3 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 3.314 ns; Loc. = LCFF_X27_Y5_N29; Fanout = 3; REG Node = 'FSK_Demod:inst2\|m\[1\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { FSK_Demod:inst2|m[1]~205 FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.171 ns ( 35.33 % ) " "Info: Total cell delay = 1.171 ns ( 35.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.143 ns ( 64.67 % ) " "Info: Total interconnect delay = 2.143 ns ( 64.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.314 ns" { FSK_Demod:inst2|cnt[0] FSK_Demod:inst2|LessThan0~107 FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|m[1]~205 FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.314 ns" { FSK_Demod:inst2|cnt[0] {} FSK_Demod:inst2|LessThan0~107 {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|m[1]~205 {} FSK_Demod:inst2|m[1] {} } { 0.000ns 1.073ns 0.655ns 0.415ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.651ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.290 ns" { clk FSK_Mod:inst1|FSK_out FSK_Mod:inst1|FSK_out~clkctrl FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.290 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} FSK_Mod:inst1|FSK_out~clkctrl {} FSK_Demod:inst2|m[1] {} } { 0.000ns 0.000ns 0.952ns 2.713ns 0.839ns } { 0.000ns 1.150ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.102 ns" { clk FSK_Demod:inst2|cnt[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.102 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[0] {} } { 0.000ns 0.000ns 1.286ns } { 0.000ns 1.150ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.314 ns" { FSK_Demod:inst2|cnt[0] FSK_Demod:inst2|LessThan0~107 FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|m[1]~205 FSK_Demod:inst2|m[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.314 ns" { FSK_Demod:inst2|cnt[0] {} FSK_Demod:inst2|LessThan0~107 {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|m[1]~205 {} FSK_Demod:inst2|m[1] {} } { 0.000ns 1.073ns 0.655ns 0.415ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.651ns 0.108ns } "" } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
?? 快捷鍵說(shuō)明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
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顯示快捷鍵
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增大字號(hào)
Ctrl + =
減小字號(hào)
Ctrl + -