{ "Info" "ITDB_TSU_RESULT" "FSK_Mod:inst1\|FSK_out Base_Sin clk 5.599 ns register " "Info: tsu for register \"FSK_Mod:inst1\|FSK_out\" (data pin = \"Base_Sin\", clock pin = \"clk\") is 5.599 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.407 ns + Longest pin register " "Info: + Longest pin to register delay is 8.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns Base_Sin 1 PIN PIN_14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_14; Fanout = 1; PIN Node = 'Base_Sin'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Base_Sin } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 224 -120 48 240 "Base_Sin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.098 ns) + CELL(0.206 ns) 8.299 ns FSK_Mod:inst1\|FSK_out~10 2 COMB LCCOMB_X27_Y5_N18 1 " "Info: 2: + IC(7.098 ns) + CELL(0.206 ns) = 8.299 ns; Loc. = LCCOMB_X27_Y5_N18; Fanout = 1; COMB Node = 'FSK_Mod:inst1\|FSK_out~10'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.304 ns" { Base_Sin FSK_Mod:inst1|FSK_out~10 } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.407 ns FSK_Mod:inst1\|FSK_out 3 REG LCFF_X27_Y5_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.407 ns; Loc. = LCFF_X27_Y5_N19; Fanout = 2; REG Node = 'FSK_Mod:inst1\|FSK_out'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { FSK_Mod:inst1|FSK_out~10 FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.309 ns ( 15.57 % ) " "Info: Total cell delay = 1.309 ns ( 15.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.098 ns ( 84.43 % ) " "Info: Total interconnect delay = 7.098 ns ( 84.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.407 ns" { Base_Sin FSK_Mod:inst1|FSK_out~10 FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.407 ns" { Base_Sin {} Base_Sin~combout {} FSK_Mod:inst1|FSK_out~10 {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 7.098ns 0.000ns } { 0.000ns 0.995ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.768 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns clk 1 CLK PIN_132 10 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_132; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.952 ns) + CELL(0.666 ns) 2.768 ns FSK_Mod:inst1\|FSK_out 2 REG LCFF_X27_Y5_N19 2 " "Info: 2: + IC(0.952 ns) + CELL(0.666 ns) = 2.768 ns; Loc. = LCFF_X27_Y5_N19; Fanout = 2; REG Node = 'FSK_Mod:inst1\|FSK_out'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.618 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.816 ns ( 65.61 % ) " "Info: Total cell delay = 1.816 ns ( 65.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.952 ns ( 34.39 % ) " "Info: Total interconnect delay = 0.952 ns ( 34.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 0.952ns } { 0.000ns 1.150ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.407 ns" { Base_Sin FSK_Mod:inst1|FSK_out~10 FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.407 ns" { Base_Sin {} Base_Sin~combout {} FSK_Mod:inst1|FSK_out~10 {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 7.098ns 0.000ns } { 0.000ns 0.995ns 0.206ns 0.108ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 0.952ns } { 0.000ns 1.150ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Demod FSK_Demod:inst2\|Demod 11.707 ns register " "Info: tco from clock \"clk\" to destination pin \"Demod\" through register \"FSK_Demod:inst2\|Demod\" is 11.707 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.113 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.113 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns clk 1 CLK PIN_132 10 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_132; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.952 ns) + CELL(0.970 ns) 3.072 ns FSK_Demod:inst2\|cnt\[4\] 2 REG LCFF_X27_Y5_N7 4 " "Info: 2: + IC(0.952 ns) + CELL(0.970 ns) = 3.072 ns; Loc. = LCFF_X27_Y5_N7; Fanout = 4; REG Node = 'FSK_Demod:inst2\|cnt\[4\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.922 ns" { clk FSK_Demod:inst2|cnt[4] } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.053 ns) + CELL(0.624 ns) 4.749 ns FSK_Demod:inst2\|LessThan0~108 3 COMB LCCOMB_X27_Y5_N26 1 " "Info: 3: + IC(1.053 ns) + CELL(0.624 ns) = 4.749 ns; Loc. = LCCOMB_X27_Y5_N26; Fanout = 1; COMB Node = 'FSK_Demod:inst2\|LessThan0~108'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.677 ns" { FSK_Demod:inst2|cnt[4] FSK_Demod:inst2|LessThan0~108 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.686 ns) + CELL(0.650 ns) 6.085 ns FSK_Demod:inst2\|LessThan0~109 4 COMB LCCOMB_X27_Y5_N20 4 " "Info: 4: + IC(0.686 ns) + CELL(0.650 ns) = 6.085 ns; Loc. = LCCOMB_X27_Y5_N20; Fanout = 4; COMB Node = 'FSK_Demod:inst2\|LessThan0~109'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.336 ns" { FSK_Demod:inst2|LessThan0~108 FSK_Demod:inst2|LessThan0~109 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.615 ns) 7.113 ns FSK_Demod:inst2\|Demod 5 REG LCCOMB_X27_Y5_N16 1 " "Info: 5: + IC(0.413 ns) + CELL(0.615 ns) = 7.113 ns; Loc. = LCCOMB_X27_Y5_N16; Fanout = 1; REG Node = 'FSK_Demod:inst2\|Demod'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.028 ns" { FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.009 ns ( 56.36 % ) " "Info: Total cell delay = 4.009 ns ( 56.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.104 ns ( 43.64 % ) " "Info: Total interconnect delay = 3.104 ns ( 43.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.113 ns" { clk FSK_Demod:inst2|cnt[4] FSK_Demod:inst2|LessThan0~108 FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.113 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[4] {} FSK_Demod:inst2|LessThan0~108 {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.000ns 0.952ns 1.053ns 0.686ns 0.413ns } { 0.000ns 1.150ns 0.970ns 0.624ns 0.650ns 0.615ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.594 ns + Longest register pin " "Info: + Longest register to pin delay is 4.594 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FSK_Demod:inst2\|Demod 1 REG LCCOMB_X27_Y5_N16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X27_Y5_N16; Fanout = 1; REG Node = 'FSK_Demod:inst2\|Demod'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FSK_Demod:inst2|Demod } "NODE_NAME" } } { "FSK_Demod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Demod.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.318 ns) + CELL(3.276 ns) 4.594 ns Demod 2 PIN PIN_99 0 " "Info: 2: + IC(1.318 ns) + CELL(3.276 ns) = 4.594 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'Demod'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.594 ns" { FSK_Demod:inst2|Demod Demod } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 96 912 1088 112 "Demod" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.276 ns ( 71.31 % ) " "Info: Total cell delay = 3.276 ns ( 71.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.318 ns ( 28.69 % ) " "Info: Total interconnect delay = 1.318 ns ( 28.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.594 ns" { FSK_Demod:inst2|Demod Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.594 ns" { FSK_Demod:inst2|Demod {} Demod {} } { 0.000ns 1.318ns } { 0.000ns 3.276ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.113 ns" { clk FSK_Demod:inst2|cnt[4] FSK_Demod:inst2|LessThan0~108 FSK_Demod:inst2|LessThan0~109 FSK_Demod:inst2|Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.113 ns" { clk {} clk~combout {} FSK_Demod:inst2|cnt[4] {} FSK_Demod:inst2|LessThan0~108 {} FSK_Demod:inst2|LessThan0~109 {} FSK_Demod:inst2|Demod {} } { 0.000ns 0.000ns 0.952ns 1.053ns 0.686ns 0.413ns } { 0.000ns 1.150ns 0.970ns 0.624ns 0.650ns 0.615ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.594 ns" { FSK_Demod:inst2|Demod Demod } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.594 ns" { FSK_Demod:inst2|Demod {} Demod {} } { 0.000ns 1.318ns } { 0.000ns 3.276ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "FSK_Mod:inst1\|FSK_out Base_Sin clk -5.333 ns register " "Info: th for register \"FSK_Mod:inst1\|FSK_out\" (data pin = \"Base_Sin\", clock pin = \"clk\") is -5.333 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.768 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns clk 1 CLK PIN_132 10 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_132; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 128 -120 48 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.952 ns) + CELL(0.666 ns) 2.768 ns FSK_Mod:inst1\|FSK_out 2 REG LCFF_X27_Y5_N19 2 " "Info: 2: + IC(0.952 ns) + CELL(0.666 ns) = 2.768 ns; Loc. = LCFF_X27_Y5_N19; Fanout = 2; REG Node = 'FSK_Mod:inst1\|FSK_out'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.618 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.816 ns ( 65.61 % ) " "Info: Total cell delay = 1.816 ns ( 65.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.952 ns ( 34.39 % ) " "Info: Total interconnect delay = 0.952 ns ( 34.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 0.952ns } { 0.000ns 1.150ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.407 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns Base_Sin 1 PIN PIN_14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_14; Fanout = 1; PIN Node = 'Base_Sin'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Base_Sin } "NODE_NAME" } } { "FSK.bdf" "" { Schematic "E:/My_Design/FPGA/FSK/FSK.bdf" { { 224 -120 48 240 "Base_Sin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.098 ns) + CELL(0.206 ns) 8.299 ns FSK_Mod:inst1\|FSK_out~10 2 COMB LCCOMB_X27_Y5_N18 1 " "Info: 2: + IC(7.098 ns) + CELL(0.206 ns) = 8.299 ns; Loc. = LCCOMB_X27_Y5_N18; Fanout = 1; COMB Node = 'FSK_Mod:inst1\|FSK_out~10'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.304 ns" { Base_Sin FSK_Mod:inst1|FSK_out~10 } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.407 ns FSK_Mod:inst1\|FSK_out 3 REG LCFF_X27_Y5_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.407 ns; Loc. = LCFF_X27_Y5_N19; Fanout = 2; REG Node = 'FSK_Mod:inst1\|FSK_out'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { FSK_Mod:inst1|FSK_out~10 FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "FSK_Mod.vhd" "" { Text "E:/My_Design/FPGA/FSK/FSK_Mod.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.309 ns ( 15.57 % ) " "Info: Total cell delay = 1.309 ns ( 15.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.098 ns ( 84.43 % ) " "Info: Total interconnect delay = 7.098 ns ( 84.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.407 ns" { Base_Sin FSK_Mod:inst1|FSK_out~10 FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.407 ns" { Base_Sin {} Base_Sin~combout {} FSK_Mod:inst1|FSK_out~10 {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 7.098ns 0.000ns } { 0.000ns 0.995ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.768 ns" { clk FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.768 ns" { clk {} clk~combout {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 0.952ns } { 0.000ns 1.150ns 0.666ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.407 ns" { Base_Sin FSK_Mod:inst1|FSK_out~10 FSK_Mod:inst1|FSK_out } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.407 ns" { Base_Sin {} Base_Sin~combout {} FSK_Mod:inst1|FSK_out~10 {} FSK_Mod:inst1|FSK_out {} } { 0.000ns 0.000ns 7.098ns 0.000ns } { 0.000ns 0.995ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}