+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 39    ;
;                                             ;       ;
; Total combinational functions               ; 39    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 3     ;
;     -- 3 input functions                    ; 5     ;
;     -- <=2 input functions                  ; 31    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 12    ;
;     -- arithmetic mode                      ; 27    ;
;                                             ;       ;
; Total registers                             ; 27    ;
;     -- Dedicated logic registers            ; 27    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 5     ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 24    ;
; Total fan-out                               ; 143   ;
; Average fan-out                             ; 2.01  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name  ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------+--------------+
; |FSK                       ; 39 (0)            ; 27 (0)       ; 0           ; 0            ; 0       ; 0         ; 5    ; 0            ; |FSK                 ; work         ;
;    |Carrier:inst|          ; 22 (22)           ; 15 (15)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |FSK|Carrier:inst    ; work         ;
;    |FSK_Demod:inst2|       ; 16 (16)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |FSK|FSK_Demod:inst2 ; work         ;
;    |FSK_Mod:inst1|         ; 1 (1)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |FSK|FSK_Mod:inst1   ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                     ;
+----------------------------------------------------+---------------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal       ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------------+------------------------+
; FSK_Demod:inst2|Demod                              ; FSK_Demod:inst2|LessThan0 ; yes                    ;
; Number of user-specified and inferred latches = 1  ;                           ;                        ;
+----------------------------------------------------+---------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+-----------------------------------------------------------------------------+
; Registers Removed During Synthesis                                          ;
+----------------------------------------+------------------------------------+
; Register name                          ; Reason for Removal                 ;
+----------------------------------------+------------------------------------+
; Carrier:inst|cnt[0]                    ; Merged with FSK_Demod:inst2|cnt[0] ;
; Carrier:inst|cnt[1]                    ; Merged with FSK_Demod:inst2|cnt[1] ;
; Carrier:inst|cnt[2]                    ; Merged with FSK_Demod:inst2|cnt[2] ;
; Carrier:inst|cnt[3]                    ; Merged with FSK_Demod:inst2|cnt[3] ;
; Carrier:inst|cnt[4]                    ; Merged with FSK_Demod:inst2|cnt[4] ;
; Carrier:inst|cnt[5]                    ; Merged with FSK_Demod:inst2|cnt[5] ;
; Carrier:inst|cnt[6]                    ; Merged with FSK_Demod:inst2|cnt[6] ;
; Carrier:inst|cnt[7]                    ; Merged with FSK_Demod:inst2|cnt[7] ;
; Carrier:inst|cnt[23..24]               ; Lost fanout                        ;
; Total Number of Removed Registers = 10 ;                                    ;
+----------------------------------------+------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 27    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Jun 12 10:23:21 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FSK -c FSK
Info: Found 2 design units, including 1 entities, in source file FSK_Mod.vhd
    Info: Found design unit 1: FSK_Mod-behave
    Info: Found entity 1: FSK_Mod
Info: Found 2 design units, including 1 entities, in source file Carrier.vhd
    Info: Found design unit 1: Carrier-behave
    Info: Found entity 1: Carrier
Info: Found 1 design units, including 1 entities, in source file FSK.bdf
    Info: Found entity 1: FSK
Info: Found 2 design units, including 1 entities, in source file FSK_Demod.vhd
    Info: Found design unit 1: FSK_Demod-behave
    Info: Found entity 1: FSK_Demod
Info: Elaborating entity "FSK" for the top level hierarchy
Info: Elaborating entity "FSK_Mod" for hierarchy "FSK_Mod:inst1"
Info: Elaborating entity "Carrier" for hierarchy "Carrier:inst"
Info: Elaborating entity "FSK_Demod" for hierarchy "FSK_Demod:inst2"
Warning (10492): VHDL Process Statement warning at FSK_Demod.vhd(26): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at FSK_Demod.vhd(23): inferring latch(es) for signal or variable "Demod", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "Demod" at FSK_Demod.vhd(23)
Info: Duplicate registers merged to single register
    Info: Duplicate register "Carrier:inst|cnt[0]" merged to single register "FSK_Demod:inst2|cnt[0]"
    Info: Duplicate register "Carrier:inst|cnt[1]" merged to single register "FSK_Demod:inst2|cnt[1]"
    Info: Duplicate register "Carrier:inst|cnt[2]" merged to single register "FSK_Demod:inst2|cnt[2]"
    Info: Duplicate register "Carrier:inst|cnt[3]" merged to single register "FSK_Demod:inst2|cnt[3]"
    Info: Duplicate register "Carrier:inst|cnt[4]" merged to single register "FSK_Demod:inst2|cnt[4]"
    Info: Duplicate register "Carrier:inst|cnt[5]" merged to single register "FSK_Demod:inst2|cnt[5]"
    Info: Duplicate register "Carrier:inst|cnt[6]" merged to single register "FSK_Demod:inst2|cnt[6]"
    Info: Duplicate register "Carrier:inst|cnt[7]" merged to single register "FSK_Demod:inst2|cnt[7]"
Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below.
    Info: Register "Carrier:inst|cnt[23]" lost all its fanouts during netlist optimizations.
    Info: Register "Carrier:inst|cnt[24]" lost all its fanouts during netlist optimizations.
Info: Implemented 44 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 3 output pins
    Info: Implemented 39 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Thu Jun 12 10:23:23 2008
    Info: Elapsed time: 00:00:02