---------------------------------------------------------------------------------                                                                           ----          X       X   XXXXXX    XXXXXX    XXXXXX    XXXXXX      X          ----          XX     XX  X      X  X      X  X      X  X           XX          ----          X X   X X  X         X      X  X      X  X          X X          ----          X  X X  X  X         X      X  X      X  X         X  X          ----          X   X   X  X          XXXXXX   X      X   XXXXXX      X          ----          X       X  X         X      X  X      X         X     X          ----          X       X  X         X      X  X      X         X     X          ----          X       X  X      X  X      X  X      X         X     X          ----          X       X   XXXXXX    XXXXXX    XXXXXX    XXXXXX      X          ----                                                                           ----                                                                           ----                       O R E G A N O   S Y S T E M S                       ----                                                                           ----                            Design & Consulting                            ----                                                                           -----------------------------------------------------------------------------------                                                                           ----         Web:           http://www.oregano.at/                             ----                                                                           ----         Contact:       mc8051@oregano.at                                  ----                                                                           -----------------------------------------------------------------------------------                                                                           ----  MC8051 - VHDL 8051 Microcontroller IP Core                               ----  Copyright (C) 2001 OREGANO SYSTEMS                                       ----                                                                           ----  This library is free software; you can redistribute it and/or            ----  modify it under the terms of the GNU Lesser General Public               ----  License as published by the Free Software Foundation; either             ----  version 2.1 of the License, or (at your option) any later version.       ----                                                                           ----  This library is distributed in the hope that it will be useful,          ----  but WITHOUT ANY WARRANTY; without even the implied warranty of           ----  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        ----  Lesser General Public License for more details.                          ----                                                                           ----  Full details of the license can be found in the file LGPL.TXT.           ----                                                                           ----  You should have received a copy of the GNU Lesser General Public         ----  License along with this library; if not, write to the Free Software      ----  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  ----                                                                           ---------------------------------------------------------------------------------------         Author:                 Helmut Mayrhofer----         Filename:               tb_mc8051_top_sim.vhd----         Date of Creation:       Mon Aug  9 12:14:48 1999----         Version:                $Revision: 1.2 $----         Date of Latest Version: $Date: 2002/01/07 12:16:57 $------         Description: Top level testbench for the mc8051 IP-core.---------------------------------------------------------------------------------------architecture sim of tb_mc8051_top is  signal s_p0_i : std_logic_vector(7 downto 0);  signal s_p1_i : std_logic_vector(7 downto 0);  signal s_p2_i : std_logic_vector(7 downto 0);  signal s_p3_i : std_logic_vector(7 downto 0);  signal s_p0_o : std_logic_vector(7 downto 0);  signal s_p1_o : std_logic_vector(7 downto 0);  signal s_p2_o : std_logic_vector(7 downto 0);  signal s_p3_o : std_logic_vector(7 downto 0);  signal clk   : std_logic;  signal reset : std_logic;  signal s_int0 : std_logic_vector(C_IMPL_N_EXT-1 downto 0);  signal s_int1 : std_logic_vector(C_IMPL_N_EXT-1 downto 0);  signal s_all_t0 : std_logic_vector(C_IMPL_N_TMR-1 downto 0);  signal s_all_t1 : std_logic_vector(C_IMPL_N_TMR-1 downto 0);  signal s_all_rxd   : std_logic_vector(C_IMPL_N_SIU-1 downto 0);  signal s_all_rxd_o : std_logic_vector(C_IMPL_N_SIU-1 downto 0);  signal s_all_txd   : std_logic_vector(C_IMPL_N_SIU-1 downto 0);    begin  i_mc8051_top : mc8051_top    port map (reset     => reset,              int0_i    => s_int0,              int1_i    => s_int1,              all_t0_i  => s_all_t0,              all_t1_i  => s_all_t1,              all_rxd_i => s_all_rxd,              all_rxd_o => s_all_rxd_o,              all_txd_o => s_all_txd,              clk       => clk,              p0_i      => s_p0_i,              p1_i      => s_p1_i,              p2_i      => s_p2_i,              p3_i      => s_p3_i,              p0_o      => s_p0_o,              p1_o      => s_p1_o,              p2_o      => s_p2_o,              p3_o      => s_p3_o);  -----------------------------------------------------------------------------  p_run : process  begin    ---------------------------------------------------------------------------    -- set start values and perform reset    ---------------------------------------------------------------------------    s_p0_i <= "00000000";    s_p1_i <= "00000000";    s_p2_i <= "00000000";    s_p3_i <= "00000000";    s_int0    <= ( others => '1' );    s_int1    <= ( others => '1' );    s_all_t0  <= ( others => '0' );    s_all_t1  <= ( others => '0' );    s_all_rxd <= ( others => '0' );    reset <= '1';    wait for one_period + one_period/2 + 5 ns;    reset <= '0';    wait for one_period * 500;    wait for one_period / 2;    assert false report "END OF SIMULATION" severity failure;  end process p_run;  -----------------------------------------------------------------------------  -----------------------------------------------------------------------------  -- system clock definition  p_clock : process        variable v_loop1 : integer;      begin    clk <= '0';    wait for one_period/2;    while true loop      clk <= not clk;      wait for one_period/2;    end loop;      end process p_clock;  -----------------------------------------------------------------------------end sim;