s_det_ff0 <= '0';          s_det_ff1 <= '0';          if s_ren = '1' then                       -- sample for data bits            case s_mode is              when ("01") | ("11") =>                 if smod_i = '1' then                  if s_pre_count(3 downto 0) = conv_unsigned(7,4) or                     s_pre_count(3 downto 0) = conv_unsigned(8,4) or                     s_pre_count(3 downto 0) = conv_unsigned(9,4) then                    s_rxd_ff0 <= rxd_i;                      s_rxd_ff1 <= s_rxd_ff0;                    s_rxd_ff2 <= s_rxd_ff1;                  end if;                                else                  if s_pre_count(4 downto 0) = conv_unsigned(14,5) or                     s_pre_count(4 downto 0) = conv_unsigned(16,5) or                     s_pre_count(4 downto 0) = conv_unsigned(18,5) then                     s_rxd_ff0 <= rxd_i;                      s_rxd_ff1 <= s_rxd_ff0;                                        s_rxd_ff2 <= s_rxd_ff1;                  end if;                end if;              when ("10") =>                if smod_i = '1' then                  if s_pre_count(4 downto 0) = conv_unsigned(14,5) or                     s_pre_count(4 downto 0) = conv_unsigned(16,5) or                     s_pre_count(4 downto 0) = conv_unsigned(18,5) then                     s_rxd_ff0 <= rxd_i;                      s_rxd_ff1 <= s_rxd_ff0;                    s_rxd_ff2 <= s_rxd_ff1;                  end if;                else                  if s_pre_count(5 downto 0) = conv_unsigned(28,6) or                     s_pre_count(5 downto 0) = conv_unsigned(32,6) or                     s_pre_count(5 downto 0) = conv_unsigned(36,6) then                    s_rxd_ff0 <= rxd_i;                      s_rxd_ff1 <= s_rxd_ff0;                                        s_rxd_ff2 <= s_rxd_ff1;                  end if;                end if;              when others =>                null;            end case;          end if;        end if;      end if;    end if;  end process p_sample_rx;---------------------------------------------------------------------------------*************************** TRANSMIT ****************************************-- This is the finit state machine for the transmit shift register-------------------------------------------------------------------------------    txd_o <= s_txdm0;    p_transmit : process (clk, reset)    variable v_txstep : std_logic_vector(1 downto 0);      begin        if reset = '1' then      s_tran_state <= conv_unsigned(0, 4);      s_tran_sh    <= conv_unsigned(0, 11);      s_tran_done  <= '0';      s_txdm0 <= '1';      rxd_o   <= '0';      rxdwr_o <= '0';    else      if clk'event and clk = '1' then        -- Set default behavior        v_txstep := "00";        case s_mode is--------------------------------------------------------------------------------- MODE 0-------------------------------------------------------------------------------          when ("00") =>	                if s_tran_state = conv_unsigned(1, 4) or              s_tran_state = conv_unsigned(2, 4) or              s_tran_state = conv_unsigned(3, 4) or              s_tran_state = conv_unsigned(4, 4) or              s_tran_state = conv_unsigned(5, 4) or              s_tran_state = conv_unsigned(6, 4) or              s_tran_state = conv_unsigned(7, 4) or              s_tran_state = conv_unsigned(8, 4) or              s_recv_state = conv_unsigned(1, 4) or              s_recv_state = conv_unsigned(2, 4) or              s_recv_state = conv_unsigned(3, 4) or              s_recv_state = conv_unsigned(4, 4) or              s_recv_state = conv_unsigned(5, 4) or              s_recv_state = conv_unsigned(6, 4) or              s_recv_state = conv_unsigned(7, 4) or              s_recv_state = conv_unsigned(8, 4) then              if s_pre_count(3 downto 0) = conv_unsigned(14, 4) or                s_pre_count(3 downto 0) = conv_unsigned(6, 4) then                s_txdm0 <= not(s_txdm0);              end if;            else              s_txdm0 <= '1';            end if;            if s_m0_shift_en = '1' then              case s_tran_state is                when ("0001") =>  	-- D1                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  rxd_o                 <= s_tran_sh(1);                  rxdwr_o <= '1';                when ("0010") =>  	-- D2                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  rxd_o                 <= s_tran_sh(1);                  rxdwr_o <= '1';                when ("0011") =>  	-- D3                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  rxd_o                 <= s_tran_sh(1);                  rxdwr_o <= '1';                when ("0100") =>  	-- D4                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  rxd_o                 <= s_tran_sh(1);                  rxdwr_o <= '1';                when ("0101") =>  	-- D5                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  rxd_o                 <= s_tran_sh(1);                  rxdwr_o <= '1';                when ("0110") =>  	-- D6                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  rxd_o                 <= s_tran_sh(1);                  rxdwr_o <= '1';                when ("0111") =>  	-- D7                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  rxd_o                 <= s_tran_sh(1);                  rxdwr_o <= '1';                when ("1000") =>  	-- D8, STOP BIT                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  s_tran_done           <= '1';                  v_txstep              := "10";                  rxd_o                 <= s_tran_sh(1);                  rxdwr_o <= '1';                when others =>  	-- D0                  -- commence transmission if conditions are met                  if s_trans = '1' then                    s_tran_sh(10 downto 8) <= conv_unsigned(7, 3);                    s_tran_sh(7 downto 0)  <= unsigned(sbuf_i);                    v_txstep               := "01";                    s_tran_done            <= '0';                    rxd_o                  <= sbuf_i(0);                    rxdwr_o <= '1';                  end if;              end case;            end if;--------------------------------------------------------------------------------- MODE 1-------------------------------------------------------------------------------          when ("01") =>            rxdwr_o <= '0';            rxd_o <= '0';            case s_tran_state is              when ("0001") =>  	-- D1                if s_m13_shift_en = '1' then                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  s_txdm0               <= s_tran_sh(1);                end if;              when ("0010") =>  	-- D2                if s_m13_shift_en = '1' then                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  s_txdm0               <= s_tran_sh(1);                end if;              when ("0011") =>  	-- D3                if s_m13_shift_en = '1' then                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  s_txdm0               <= s_tran_sh(1);                end if;              when ("0100") =>  	-- D4                if s_m13_shift_en = '1' then                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  s_txdm0               <= s_tran_sh(1);                end if;              when ("0101") =>  	-- D5                if s_m13_shift_en = '1' then                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  s_txdm0               <= s_tran_sh(1);                end if;              when ("0110") =>  	-- D6                if s_m13_shift_en = '1' then                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  s_txdm0               <= s_tran_sh(1);                end if;              when ("0111") =>  	-- D7                if s_m13_shift_en = '1' then                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  s_txdm0               <= s_tran_sh(1);                end if;              when ("1000") =>  	-- D8                if s_m13_shift_en = '1' then                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  s_txdm0               <= s_tran_sh(1);                end if;              when ("1001") =>  	-- D9, set done bit                if s_m13_shift_en = '1' then                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  s_tran_done           <= '1';                  v_txstep              := "10";                  s_txdm0               <= s_tran_sh(1);                end if;              when others =>  		-- D0                -- commence transmission if conditions are met                s_txdm0 <= '1';                if s_m13_shift_en = '1' then                  if s_trans = '1' then                    s_tran_sh(10 downto 9) <= conv_unsigned(3, 2);                    s_tran_sh(8 downto 1)  <= unsigned(sbuf_i);                    s_tran_sh(0)           <= '0';                    v_txstep               := "01";                    s_tran_done            <= '0';                    s_txdm0                <= '0';                  end if;                end if;            end case;--------------------------------------------------------------------------------- MODE 2-------------------------------------------------------------------------------          when ("10") =>            rxdwr_o <= '0';            rxd_o <= '0';            case s_tran_state is              when ("0001") =>  	-- D1                if s_m2_shift_en = '1' then                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  s_txdm0               <= s_tran_sh(1);                end if;              when ("0010") =>  	-- D2                if s_m2_shift_en = '1' then                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  s_txdm0               <= s_tran_sh(1);                end if;              when ("0011") =>  	-- D3                if s_m2_shift_en = '1' then                  s_tran_sh(10)         <= '1';                  s_tran_sh(9 downto 0) <= s_tran_sh(10 downto 1);                  v_txstep              := "01";                  s_txdm0               <= s_tran_sh(1);                end if;              when ("0100") =>  	-- D4                if s_m2_shift_en = '1' then                  s_tran_sh(10)         <= '1';