dcml_data_o <= ( others => '0' );         mltplcnd_o  <= ( others => '0' );         mltplctr_o  <= ( others => '0' );         dvdnd_o     <= acc_i;         dvsor_o     <= ram_data_i;         addsub_o    <= '0';         addsub_cy_o <= '0';         opa_o       <= ( others => '0' );         opb_o       <= ( others => '0' );       when MUL_ACC_RAM =>         dcml_data_o <= ( others => '0' );         mltplcnd_o  <= acc_i;         mltplctr_o  <= ram_data_i;         dvdnd_o     <= ( others => '0' );         dvsor_o     <= ( others => '0' );         addsub_o    <= '0';         addsub_cy_o <= '0';         opa_o       <= ( others => '0' );         opb_o       <= ( others => '0' );       when INC_ACC =>         dcml_data_o <= ( others => '0' );         mltplcnd_o  <= ( others => '0' );         mltplctr_o  <= ( others => '0' );         dvdnd_o     <= ( others => '0' );         dvsor_o     <= ( others => '0' );         addsub_o    <= '1';         addsub_cy_o <= '0';         opa_o       <= acc_i;         opb_o       <= std_logic_vector(conv_unsigned(1, DWIDTH));       when INC_RAM =>         dcml_data_o <= ( others => '0' );         mltplcnd_o  <= ( others => '0' );         mltplctr_o  <= ( others => '0' );         dvdnd_o     <= ( others => '0' );         dvsor_o     <= ( others => '0' );         addsub_o    <= '1';         addsub_cy_o <= '0';         opa_o       <= ram_data_i;         opb_o       <= std_logic_vector(conv_unsigned(1, DWIDTH));       when DEC_ACC =>         dcml_data_o <= ( others => '0' );         mltplcnd_o  <= ( others => '0' );         mltplctr_o  <= ( others => '0' );         dvdnd_o     <= ( others => '0' );         dvsor_o     <= ( others => '0' );         addsub_o    <= '0';         addsub_cy_o <= '0';         opa_o       <= acc_i;         opb_o       <= std_logic_vector(conv_unsigned(1, DWIDTH));       when DEC_RAM =>         dcml_data_o <= ( others => '0' );         mltplcnd_o  <= ( others => '0' );         mltplctr_o  <= ( others => '0' );         dvdnd_o     <= ( others => '0' );         dvsor_o     <= ( others => '0' );         addsub_o    <= '0';         addsub_cy_o <= '0';         opa_o       <= ram_data_i;         opb_o       <= std_logic_vector(conv_unsigned(1, DWIDTH));       when SUB_ACC_RAM =>         dcml_data_o <= ( others => '0' );         mltplcnd_o  <= ( others => '0' );         mltplctr_o  <= ( others => '0' );         dvdnd_o     <= ( others => '0' );         dvsor_o     <= ( others => '0' );         addsub_o    <= '0';         addsub_cy_o <= cy_i((DWIDTH-1)/4);         opa_o       <= acc_i;         opb_o       <= ram_data_i;       when SUB_ACC_ROM =>         dcml_data_o <= ( others => '0' );         mltplcnd_o  <= ( others => '0' );         mltplctr_o  <= ( others => '0' );         dvdnd_o     <= ( others => '0' );         dvsor_o     <= ( others => '0' );         addsub_o    <= '0';         addsub_cy_o <= cy_i((DWIDTH-1)/4);         opa_o       <= acc_i;         opb_o       <= rom_data_i;       when ADD_ACC_RAM =>         dcml_data_o <= ( others => '0' );         mltplcnd_o  <= ( others => '0' );         mltplctr_o  <= ( others => '0' );         dvdnd_o     <= ( others => '0' );         dvsor_o     <= ( others => '0' );         addsub_o    <= '1';         addsub_cy_o <= '0';         opa_o       <= acc_i;         opb_o       <= ram_data_i;       when ADD_ACC_ROM =>         dcml_data_o <= ( others => '0' );         mltplcnd_o  <= ( others => '0' );         mltplctr_o  <= ( others => '0' );         dvdnd_o     <= ( others => '0' );         dvsor_o     <= ( others => '0' );         addsub_o    <= '1';         addsub_cy_o <= '0';         opa_o       <= acc_i;         opb_o       <= rom_data_i;       when ADDC_ACC_RAM =>         dcml_data_o <= ( others => '0' );         mltplcnd_o  <= ( others => '0' );         mltplctr_o  <= ( others => '0' );         dvdnd_o     <= ( others => '0' );         dvsor_o     <= ( others => '0' );         addsub_o    <= '1';         addsub_cy_o <= cy_i((DWIDTH-1)/4);         opa_o       <= acc_i;         opb_o       <= ram_data_i;       when ADDC_ACC_ROM =>         dcml_data_o <= ( others => '0' );         mltplcnd_o  <= ( others => '0' );         mltplctr_o  <= ( others => '0' );         dvdnd_o     <= ( others => '0' );         dvsor_o     <= ( others => '0' );         addsub_o    <= '1';         addsub_cy_o <= cy_i((DWIDTH-1)/4);         opa_o       <= acc_i;         opb_o       <= rom_data_i;       when others =>         dcml_data_o <= ( others => '0' );         mltplcnd_o  <= ( others => '0' );         mltplctr_o  <= ( others => '0' );         dvdnd_o     <= ( others => '0' );         dvsor_o     <= ( others => '0' );         addsub_o    <= '0';         addsub_cy_o <= '0';         opa_o       <= ( others => '0' );         opb_o       <= ( others => '0' );    end case;  end process p_ext_mux;  -- Multiplex the results for all the units contributing to the ALU.  p_rslt_mux : process (ram_data_i,                        cy_i,                        ov_i,                        product_i,                        qutnt_i,                        rmndr_i,                        result_i,                        new_cy_i,			addsub_rslt_i,			addsub_cy_i,			addsub_ov_i,                        dcml_data_i,                        dcml_cy_i,                        cmd_i)  begin    case cmd_i is       when DA          =>	 if (C_IMPL_DA /= 0) then           result_a_o         <= dcml_data_i;           result_b_o         <= ( others => '0' );           cy_o               <= cy_i;           cy_o((DWIDTH-1)/4) <= dcml_cy_i;           ov_o               <= ov_i;	 else             result_a_o         <= ( others => '0' );           result_b_o         <= ( others => '0' );           cy_o               <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);           ov_o               <= '0';	 end if;       when DIV_ACC_RAM =>	 if (C_IMPL_DIV /= 0) then           result_a_o         <= qutnt_i;           result_b_o         <= rmndr_i;           cy_o               <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);           if ram_data_i = conv_std_logic_vector(0,DWIDTH) then             ov_o             <= '1';           else             ov_o             <= '0';           end if;	 else           result_a_o         <= ( others => '0' );           result_b_o         <= ( others => '0' );           cy_o               <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);	   ov_o               <= '0';	 end if;       when MUL_ACC_RAM =>	 if (C_IMPL_MUL /= 0) then           result_a_o         <= product_i(DWIDTH-1 downto 0);           result_b_o         <= product_i(DWIDTH*2-1 downto DWIDTH);           cy_o               <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);           if product_i(DWIDTH*2-1 downto DWIDTH)               = conv_std_logic_vector(0, DWIDTH) then             ov_o             <= '0';           else             ov_o             <= '1';           end if;	 else           result_a_o         <= ( others => '0' );           result_b_o         <= ( others => '0' );           cy_o               <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);           ov_o               <= '0';	 end if;       when SUB_ACC_RAM | SUB_ACC_ROM | ADD_ACC_RAM | ADD_ACC_ROM |	    ADDC_ACC_RAM | ADDC_ACC_ROM  =>         result_a_o         <= addsub_rslt_i;         result_b_o         <= ( others => '0' );         cy_o               <= addsub_cy_i;         ov_o               <= addsub_ov_i;       when INC_ACC | INC_RAM | DEC_ACC | DEC_RAM =>         result_a_o         <= addsub_rslt_i;         result_b_o         <= ( others => '0' );         cy_o               <= cy_i;         ov_o               <= addsub_ov_i;	        when others      =>         result_a_o         <= result_i;         result_b_o         <= ( others => '0' );         cy_o               <= new_cy_i;         ov_o               <= ov_i;    end case;  end process p_rslt_mux;end rtl;