library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MBUS is	port(	D_IN: in std_logic_vector(20 downto 0);		D_OUT_A: out std_logic_vector(4 downto 0);		D_OUT_B: out std_logic_vector(15 downto 0) );end MBUS;architecture ALG of MBUS is	begin	process(D_IN)	begin		for INDEX in 0 to 15 loop			D_OUT_B(INDEX)<=D_IN(INDEX);					end loop;		for INDEX in 0 to 4 loop			D_OUT_A(INDEX)<=D_IN(INDEX+16);		end loop;			end process;	end ALG;