?? jw.map.rpt
字號:
Analysis & Synthesis report for JW
Tue Nov 27 14:38:54 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. User-Specified and Inferred Latches
8. General Register Statistics
9. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Nov 27 14:38:54 2007 ;
; Quartus II Version ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name ; JW ;
; Top-level Entity Name ; JW ;
; Family ; ACEX1K ;
; Total logic elements ; 10 ;
; Total pins ; 10 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+------------------------------------------+
+-------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------+----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------+----------------+---------------+
; Device ; EP1K100QC208-3 ; ;
; Top-level entity name ; JW ; JW ;
; Family name ; ACEX1K ; Stratix II ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area ; Area ;
; Carry Chain Length -- FLEX 10K ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+----------------------------------------------------------+----------------+---------------+
+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; JW.vhd ; yes ; User VHDL File ; E:/JW/JW.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+--------------------------------+------------+
; Resource ; Usage ;
+--------------------------------+------------+
; Total logic elements ; 10 ;
; Total combinational functions ; 10 ;
; -- Total 4-input functions ; 1 ;
; -- Total 3-input functions ; 8 ;
; -- Total 2-input functions ; 1 ;
; -- Total 1-input functions ; 0 ;
; -- Total 0-input functions ; 0 ;
; Total registers ; 0 ;
; I/O pins ; 10 ;
; Maximum fan-out node ; ZHUANG[1] ;
; Maximum fan-out ; 4 ;
; Total fan-out ; 33 ;
; Average fan-out ; 1.65 ;
+--------------------------------+------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |JW ; 10 (10) ; 0 ; 0 ; 10 ; 10 (10) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |JW ; work ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; JW1$latch ; Mux3 ; yes ;
; JW2$latch ; Mux3 ; yes ;
; JW3$latch ; Mux3 ; yes ;
; Number of user-specified and inferred latches = 3 ; ; ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Tue Nov 27 14:38:52 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off JW -c JW
Info: Found 2 design units, including 1 entities, in source file JW.vhd
Info: Found design unit 1: JW-behav
Info: Found entity 1: JW
Info: Elaborating entity "JW" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at JW.vhd(11): inferring latch(es) for signal or variable "JW1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at JW.vhd(11): inferring latch(es) for signal or variable "JW2", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at JW.vhd(11): inferring latch(es) for signal or variable "JW3", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "JW3" at JW.vhd(11)
Info (10041): Inferred latch for "JW2" at JW.vhd(11)
Info (10041): Inferred latch for "JW1" at JW.vhd(11)
Warning: Latch JW1$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal ZHUANG[2]
Warning: Latch JW2$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal ZHUANG[2]
Warning: Latch JW3$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal ZHUANG[2]
Info: Implemented 20 device resources after synthesis - the final resource count might be different
Info: Implemented 7 input pins
Info: Implemented 3 output pins
Info: Implemented 10 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
Info: Allocated 145 megabytes of memory during processing
Info: Processing ended: Tue Nov 27 14:38:55 2007
Info: Elapsed time: 00:00:03
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -