LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY sample IS
		PORT(a, b:IN STD_LOGIC;
			   q:OUT STD_LOGIC);
END sample;
ARCHITECTURE behav OF sample IS
	SIGNAL c,d:STD_LOGIC;
BEGIN
	c<=NOT(a);
	d<=NOT(b AND c);
	q<=c AND d;
END behav;