--MOORE 狀態機設計--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--*********************
ENTITY demo IS
  		PORT(
		clk,in1,reset: IN	std_logic;
				out1: OUT	std_logic_vector(3 downto 0));
END demo;
--****************************
ARCHITECTURE moore OF demo IS
    type state_type is (s0,s1,s2,s3);
    SIGNAL state:state_type;
	BEGIN
     demo_process:process(clk,reset)
    begin
      if reset='1'then
         state<=s0;
    elsif clk'event and clk='1'then
     case state is
       when s0=>if in1='1'then
                    state<=s1;
                end if;
       when s1=>if in1='0'then
                    state<=s2;
                end if;
       when s2=>if in1='1'then
                    state<=s3;
                end if;
       when s3=>if in1='0'then
                    state<=s0;
                end if;
     end case;
    end if;
   end process;
output_p:process(state)
begin
case state is
      when s0 =>out1<="0000";
      when s1 =>out1<="1001";
      when s2 =>out1<="1100";
      when s3 =>out1<="1111";
      when others =>out1<="XXXX";
end case;
end process;
end moore;