?? uart_tran.v
字號:
module uart_tran (clk,reset,wr_en,data,data_out,complete,clk_equ);
input clk,reset,wr_en;
input [7:0] data;
output data_out;
output complete;
output clk_equ;
reg[15:0] cnt;
reg [9:0]data_reg;
//reg [9:0]data_reg2;
reg complete;
reg data_out;
reg contral;
wire shift_done;
wire clk_equ;
reg [3:0] i;
parameter COUNT = 16'd3;
parameter [2:0]
idle=3'b000,
start=3'b001,
transition=3'b010,
stop=3'b100;
/**************************************/
always@(posedge clk)
begin
if(clk_equ)
cnt = 16'd0;
else
cnt = cnt+1'b1;
end
assign clk_equ = (cnt == COUNT);
/**************************************/
always@(posedge clk or posedge reset)
begin
if(reset)
data_reg<=10'b0;
else //有數據寫入緩存
begin
if(wr_en)
begin
data_reg = {1'b1,data[7:0],1'b0}; //讀入數據,并把緩存組成一幀數據,10位
contral=1'b1;
end
else
begin
if(complete)
contral=1'b0;
end
end
end
always@(posedge clk or posedge reset)
begin
if(reset)
begin
data_out<=1;
complete<=0;
i<=4'h0;
end
else
begin
if(clk_equ)
begin
if(i<4'd10&&contral==1)
begin
data_out<=data_reg[i];
i<=i+4'h1;
complete<=0;
end
else
begin
i<=4'd0;
complete<=1;
end
end
end
end
endmodule
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