?? uart_tran.sim.rpt
字號:
; |uart_tran|Add0~245 ; |uart_tran|Add0~246COUT1 ; cout1 ;
; |uart_tran|Add0~247 ; |uart_tran|Add0~247 ; combout ;
; |uart_tran|Add0~247 ; |uart_tran|Add0~248 ; cout0 ;
; |uart_tran|Add0~247 ; |uart_tran|Add0~248COUT1 ; cout1 ;
; |uart_tran|Add0~249 ; |uart_tran|Add0~249 ; combout ;
; |uart_tran|Add0~249 ; |uart_tran|Add0~250 ; cout0 ;
; |uart_tran|Add0~249 ; |uart_tran|Add0~250COUT1 ; cout1 ;
; |uart_tran|Add0~251 ; |uart_tran|Add0~251 ; combout ;
; |uart_tran|Add0~251 ; |uart_tran|Add0~252 ; cout ;
; |uart_tran|Add0~253 ; |uart_tran|Add0~253 ; combout ;
; |uart_tran|Add0~253 ; |uart_tran|Add0~254 ; cout0 ;
; |uart_tran|Add0~253 ; |uart_tran|Add0~254COUT1 ; cout1 ;
; |uart_tran|Add0~255 ; |uart_tran|Add0~255 ; combout ;
; |uart_tran|Add0~255 ; |uart_tran|Add0~256 ; cout0 ;
; |uart_tran|Add0~255 ; |uart_tran|Add0~256COUT1 ; cout1 ;
; |uart_tran|Add0~257 ; |uart_tran|Add0~257 ; combout ;
; |uart_tran|Add0~257 ; |uart_tran|Add0~258 ; cout0 ;
; |uart_tran|Add0~257 ; |uart_tran|Add0~258COUT1 ; cout1 ;
; |uart_tran|Add0~259 ; |uart_tran|Add0~259 ; combout ;
; |uart_tran|Add0~259 ; |uart_tran|Add0~260 ; cout0 ;
; |uart_tran|Add0~259 ; |uart_tran|Add0~260COUT1 ; cout1 ;
; |uart_tran|Add0~261 ; |uart_tran|Add0~261 ; combout ;
; |uart_tran|Add0~261 ; |uart_tran|Add0~262 ; cout ;
; |uart_tran|Add0~263 ; |uart_tran|Add0~263 ; combout ;
; |uart_tran|Add0~263 ; |uart_tran|Add0~264 ; cout0 ;
; |uart_tran|Add0~263 ; |uart_tran|Add0~264COUT1 ; cout1 ;
; |uart_tran|Add0~265 ; |uart_tran|Add0~265 ; combout ;
; |uart_tran|Add0~265 ; |uart_tran|Add0~266 ; cout0 ;
; |uart_tran|Add0~265 ; |uart_tran|Add0~266COUT1 ; cout1 ;
; |uart_tran|Add0~267 ; |uart_tran|Add0~267 ; combout ;
; |uart_tran|cnt[2] ; |uart_tran|cnt[2] ; regout ;
; |uart_tran|cnt[3] ; |uart_tran|cnt[3] ; regout ;
; |uart_tran|cnt[5] ; |uart_tran|cnt[5] ; regout ;
; |uart_tran|cnt[6] ; |uart_tran|cnt[6] ; regout ;
; |uart_tran|cnt[7] ; |uart_tran|cnt[7] ; regout ;
; |uart_tran|cnt[4] ; |uart_tran|Equal0~148 ; combout ;
; |uart_tran|cnt[4] ; |uart_tran|cnt[4] ; regout ;
; |uart_tran|cnt[9] ; |uart_tran|cnt[9] ; regout ;
; |uart_tran|cnt[10] ; |uart_tran|cnt[10] ; regout ;
; |uart_tran|cnt[11] ; |uart_tran|cnt[11] ; regout ;
; |uart_tran|cnt[8] ; |uart_tran|Equal0~149 ; combout ;
; |uart_tran|cnt[8] ; |uart_tran|cnt[8] ; regout ;
; |uart_tran|cnt[13] ; |uart_tran|cnt[13] ; regout ;
; |uart_tran|cnt[14] ; |uart_tran|cnt[14] ; regout ;
; |uart_tran|cnt[15] ; |uart_tran|cnt[15] ; regout ;
; |uart_tran|cnt[12] ; |uart_tran|Equal0~150 ; combout ;
; |uart_tran|cnt[12] ; |uart_tran|cnt[12] ; regout ;
; |uart_tran|data_reg[2] ; |uart_tran|data_reg[2] ; regout ;
; |uart_tran|reset ; |uart_tran|reset~corein ; combout ;
; |uart_tran|data[7] ; |uart_tran|data[7]~corein ; combout ;
; |uart_tran|data[1] ; |uart_tran|data[1]~corein ; combout ;
; |uart_tran|data[5] ; |uart_tran|data[5]~corein ; combout ;
+------------------------+---------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+--------------------------+---------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------------+---------------------------+------------------+
; |uart_tran|Add0~241 ; |uart_tran|Add0~242 ; cout ;
; |uart_tran|Add0~243 ; |uart_tran|Add0~243 ; combout ;
; |uart_tran|Add0~243 ; |uart_tran|Add0~244 ; cout0 ;
; |uart_tran|Add0~243 ; |uart_tran|Add0~244COUT1 ; cout1 ;
; |uart_tran|Add0~245 ; |uart_tran|Add0~245 ; combout ;
; |uart_tran|Add0~245 ; |uart_tran|Add0~246 ; cout0 ;
; |uart_tran|Add0~245 ; |uart_tran|Add0~246COUT1 ; cout1 ;
; |uart_tran|Add0~247 ; |uart_tran|Add0~247 ; combout ;
; |uart_tran|Add0~247 ; |uart_tran|Add0~248 ; cout0 ;
; |uart_tran|Add0~247 ; |uart_tran|Add0~248COUT1 ; cout1 ;
; |uart_tran|Add0~249 ; |uart_tran|Add0~249 ; combout ;
; |uart_tran|Add0~249 ; |uart_tran|Add0~250 ; cout0 ;
; |uart_tran|Add0~249 ; |uart_tran|Add0~250COUT1 ; cout1 ;
; |uart_tran|Add0~251 ; |uart_tran|Add0~251 ; combout ;
; |uart_tran|Add0~251 ; |uart_tran|Add0~252 ; cout ;
; |uart_tran|Add0~253 ; |uart_tran|Add0~253 ; combout ;
; |uart_tran|Add0~253 ; |uart_tran|Add0~254 ; cout0 ;
; |uart_tran|Add0~253 ; |uart_tran|Add0~254COUT1 ; cout1 ;
; |uart_tran|Add0~255 ; |uart_tran|Add0~255 ; combout ;
; |uart_tran|Add0~255 ; |uart_tran|Add0~256 ; cout0 ;
; |uart_tran|Add0~255 ; |uart_tran|Add0~256COUT1 ; cout1 ;
; |uart_tran|Add0~257 ; |uart_tran|Add0~257 ; combout ;
; |uart_tran|Add0~257 ; |uart_tran|Add0~258 ; cout0 ;
; |uart_tran|Add0~257 ; |uart_tran|Add0~258COUT1 ; cout1 ;
; |uart_tran|Add0~259 ; |uart_tran|Add0~259 ; combout ;
; |uart_tran|Add0~259 ; |uart_tran|Add0~260 ; cout0 ;
; |uart_tran|Add0~259 ; |uart_tran|Add0~260COUT1 ; cout1 ;
; |uart_tran|Add0~261 ; |uart_tran|Add0~261 ; combout ;
; |uart_tran|Add0~261 ; |uart_tran|Add0~262 ; cout ;
; |uart_tran|Add0~263 ; |uart_tran|Add0~263 ; combout ;
; |uart_tran|Add0~263 ; |uart_tran|Add0~264 ; cout0 ;
; |uart_tran|Add0~263 ; |uart_tran|Add0~264COUT1 ; cout1 ;
; |uart_tran|Add0~265 ; |uart_tran|Add0~265 ; combout ;
; |uart_tran|Add0~265 ; |uart_tran|Add0~266 ; cout0 ;
; |uart_tran|Add0~265 ; |uart_tran|Add0~266COUT1 ; cout1 ;
; |uart_tran|Add0~267 ; |uart_tran|Add0~267 ; combout ;
; |uart_tran|complete~reg0 ; |uart_tran|complete~reg0 ; regout ;
; |uart_tran|cnt[2] ; |uart_tran|cnt[2] ; regout ;
; |uart_tran|cnt[3] ; |uart_tran|cnt[3] ; regout ;
; |uart_tran|cnt[5] ; |uart_tran|cnt[5] ; regout ;
; |uart_tran|cnt[6] ; |uart_tran|cnt[6] ; regout ;
; |uart_tran|cnt[7] ; |uart_tran|cnt[7] ; regout ;
; |uart_tran|cnt[4] ; |uart_tran|Equal0~148 ; combout ;
; |uart_tran|cnt[4] ; |uart_tran|cnt[4] ; regout ;
; |uart_tran|cnt[9] ; |uart_tran|cnt[9] ; regout ;
; |uart_tran|cnt[10] ; |uart_tran|cnt[10] ; regout ;
; |uart_tran|cnt[11] ; |uart_tran|cnt[11] ; regout ;
; |uart_tran|cnt[8] ; |uart_tran|Equal0~149 ; combout ;
; |uart_tran|cnt[8] ; |uart_tran|cnt[8] ; regout ;
; |uart_tran|cnt[13] ; |uart_tran|cnt[13] ; regout ;
; |uart_tran|cnt[14] ; |uart_tran|cnt[14] ; regout ;
; |uart_tran|cnt[15] ; |uart_tran|cnt[15] ; regout ;
; |uart_tran|cnt[12] ; |uart_tran|Equal0~150 ; combout ;
; |uart_tran|cnt[12] ; |uart_tran|cnt[12] ; regout ;
; |uart_tran|data_reg[9] ; |uart_tran|data_reg[9] ; regout ;
; |uart_tran|data_reg[2] ; |uart_tran|data_reg[2] ; regout ;
; |uart_tran|data_reg[4] ; |uart_tran|data_reg[4] ; regout ;
; |uart_tran|data_reg[7] ; |uart_tran|data_reg[7] ; regout ;
; |uart_tran|complete ; |uart_tran|complete ; padio ;
; |uart_tran|data[7] ; |uart_tran|data[7]~corein ; combout ;
; |uart_tran|data[1] ; |uart_tran|data[1]~corein ; combout ;
; |uart_tran|data[5] ; |uart_tran|data[5]~corein ; combout ;
+--------------------------+---------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Fri Oct 24 09:08:39 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off uart_tran -c uart_tran
Info: Using vector source file "E:/FPGA_Project/uart_tran/uart_tran.vwf"
Warning: Compiler packed, optimized or synthesized away node "data_reg[0]". Ignored vector source file node.
Info: Inverted registers were found during simulation
Info: Register: |uart_tran|data_out~reg0
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 32.26 %
Info: Number of transitions in simulation is 1325
Info: Quartus II Simulator was successful. 0 errors, 1 warning
Info: Allocated 100 megabytes of memory during processing
Info: Processing ended: Fri Oct 24 09:08:41 2008
Info: Elapsed time: 00:00:02
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