LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TESTCTL IS
    PORT (CLKK : IN STD_LOGIC;  
          CNT_EN,RST_CNT,LOAD : OUT STD_LOGIC);     
 END ENTITY TESTCTL;
ARCHITECTURE behav OF TESTCTL IS
    SIGNAL DIV2CLK : STD_LOGIC;
BEGIN
   PROCESS( CLKK )
    BEGIN
      IF CLKK'EVENT AND CLKK = '1' THEN  DIV2CLK <= NOT DIV2CLK;
     END IF;
    END PROCESS;
    PROCESS (CLKK, DIV2CLK)
    BEGIN
        IF CLKK='0' AND Div2CLK='0' THEN  RST_CNT <= '1';
        ELSE  RST_CNT <= '0';   END IF;
    END PROCESS;
      LOAD  <= NOT DIV2CLK ;    CNT_EN <= DIV2CLK;
END ARCHITECTURE behav;