?? reg4b.vhd
字號:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG4B IS
PORT ( LOAD : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END REG4B;
ARCHITECTURE behav OF REG4B IS
BEGIN
PROCESS(LOAD, DIN)
BEGIN
IF LOAD'EVENT AND LOAD = '1' THEN DOUT <= DIN;
END IF;
END PROCESS;
END behav;
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