library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port (clk,rst,en:in std_logic;
cq: out std_logic_vector(3 downto 0);
cout:out std_logic);
end cnt10;
architecture behav of cnt10 is
begin
process (clk,rst,en)
variable cqi:std_logic_vector(3 downto 0);
begin
if rst='1' then cqi:=(others=>'0');
elsif clk'event and clk='1' then
if en='1'then 
if cqi<9 then cqi:=cqi+1;
else cqi:=(others =>'0');
end if;
end if;
end if;
if cqi=9 then cout<='1';
else cout <='0';
end if;
cq<=cqi;
end process;
end behav;