module sequence_inspector (reset,clk,signalin,signalout);
  input  reset,clk,signalin;
  output signalout;
  reg[2:0] state;
    parameter 
      idle=3'd0,
      a=3'd1,
	  b=3'd2,
	  c=3'd3,
	  d=3'd4,
	  e=3'd5;

	assign signalout=(state== e && signalin == 0)?1:0;

	always @(posedge clk)
	  if(reset)
	    begin
		  state<=idle;
		end
      else 
	    begin
		  casex(state)
		    idle:
			  begin
			    if(signalin==1)
				  state<=a;
				else
				  state<=idle;
			  end
			a:
			  begin
			    if(signalin==0)
				  state<=b;
                else
				  state<=a;
		      end
            b:
              begin
			    if(signalin==0)
				  state<=c;
				else
				  state<=a;
			  end
			c:
              begin
  			    if(signalin==1)
				  state<=d;
				else
				  state<=idle;
			  end
			d:
			  begin
			    if(signalin==0)
				  state<=e;
				else
				  state<=a;
			  end
			e:
			  begin
			    if(signalin==0)
				  state<=c;
				else
				  state<=a;
			  end
			default:
			  state<=idle;
		  endcase
		end
	endmodule