--A1L132 is txd_buf[3]~1753
--operation mode is normal

A1L132 = state_tras[2] # !state_tras[0] # !state_tras[3];


--A1L232 is txd_buf[3]~1755
--operation mode is normal

A1L232 = state_tras[0] & state_tras[3] & (state_tras[2] $ state_tras[1]) # !state_tras[0] & (state_tras[3] $ (!state_tras[2] & !state_tras[1]));


--key_entry1 is key_entry1
--operation mode is normal

key_entry1_lut_out = key_entry1 # !key_input & (!A1L921);
key_entry1 = DFFEAS(key_entry1_lut_out, clk, VCC, , , ~GND, , !rst, key_entry2);


--A1L332 is txd_buf[3]~1756
--operation mode is normal

A1L332 = key_entry2 & !A1L232 & A1L131 # !key_entry2 & (key_entry1);


--A1L67 is div8_tras_reg[2]~59
--operation mode is normal

A1L67 = div8_tras_reg[1] & div8_tras_reg[0] & trasstart;


--A1L47 is div8_tras_reg[1]~60
--operation mode is normal

A1L47 = div8_tras_reg[0] & trasstart;


--A1L6 is Select~2999
--operation mode is normal

A1L6 = !state_tras[3] & !state_tras[0] & !state_tras[2] & !state_tras[1];


--A1L7 is Select~3000
--operation mode is normal

A1L7 = trasstart # !send_state[1] # !send_state[2] # !send_state[0];


--A1L432 is txd_buf[3]~1757
--operation mode is normal

A1L432 = state_tras[2] & (!state_tras[0] # !state_tras[1]) # !state_tras[2] & state_tras[1];


--A1L8 is Select~3001
--operation mode is normal

A1L8 = A1L131 & A1L432 # !A1L131 & (trasstart & !A1L3);


--A1L9 is Select~3003
--operation mode is normal

A1L9 = state_tras[1] & (!state_tras[3]) # !state_tras[1] & (state_tras[2] & (!state_tras[3]) # !state_tras[2] & (state_tras[0] # state_tras[3]));


--A1L422 is trasstart~39
--operation mode is normal

A1L422 = key_entry2 & (!A1L9);


--A1L51 is add~1062
--operation mode is normal

A1L51 = div8_tras_reg[2] & div8_tras_reg[1] & div8_tras_reg[0] & state_tras[0];


--A1L502 is send_state[2]~0
--operation mode is normal

A1L502 = key_entry2 & state_tras[2] & A1L602 & A1L51;


--A1L702 is send_state[2]~97
--operation mode is normal

A1L702 = send_state[0] & send_state[1] & A1L502;


--A1L802 is send_state[2]~98
--operation mode is normal

A1L802 = send_state[0] & A1L502;


--A1L01 is Select~3005
--operation mode is normal

A1L01 = state_tras[0] & state_tras[1];


--A1L11 is Select~3006
--operation mode is normal

A1L11 = state_tras[3] & (state_tras[1] & (!state_tras[0] # !state_tras[2]) # !state_tras[1] & state_tras[2]);


--A1L21 is Select~3007
--operation mode is normal

A1L21 = state_tras[0] & (state_tras[1] $ !state_tras[2] # !state_tras[3]);


--A1L31 is Select~3008
--operation mode is normal

A1L31 = A1L11 & A1L51 & !A1L21 # !A1L11 & (A1L21);


--div_reg[2] is div_reg[2]
--operation mode is arithmetic

div_reg[2]_carry_eqn = A1L18;
div_reg[2]_lut_out = div_reg[2] $ (!div_reg[2]_carry_eqn);
div_reg[2] = DFFEAS(div_reg[2]_lut_out, clk, VCC, , , , , A1L29, );

--A1L38 is div_reg[2]~342
--operation mode is arithmetic

A1L38 = CARRY(div_reg[2] & (!A1L18));


--div_reg[3] is div_reg[3]
--operation mode is arithmetic

div_reg[3]_carry_eqn = A1L38;
div_reg[3]_lut_out = div_reg[3] $ (div_reg[3]_carry_eqn);
div_reg[3] = DFFEAS(div_reg[3]_lut_out, clk, VCC, , , , , A1L29, );

--A1L58 is div_reg[3]~346
--operation mode is arithmetic

A1L58 = CARRY(!A1L38 # !div_reg[3]);


--div_reg[0] is div_reg[0]
--operation mode is arithmetic

div_reg[0]_lut_out = !div_reg[0];
div_reg[0] = DFFEAS(div_reg[0]_lut_out, clk, VCC, , , , , A1L29, );

--A1L97 is div_reg[0]~350
--operation mode is arithmetic

A1L97 = CARRY(div_reg[0]);


--div_reg[1] is div_reg[1]
--operation mode is arithmetic

div_reg[1]_carry_eqn = A1L97;
div_reg[1]_lut_out = div_reg[1] $ (div_reg[1]_carry_eqn);
div_reg[1] = DFFEAS(div_reg[1]_lut_out, clk, VCC, , , , , A1L29, );

--A1L18 is div_reg[1]~354
--operation mode is arithmetic

A1L18 = CARRY(!A1L97 # !div_reg[1]);


--A1L231 is reduce_nor~319
--operation mode is normal

A1L231 = div_reg[2] # div_reg[3] # !div_reg[1] # !div_reg[0];


--div_reg[4] is div_reg[4]
--operation mode is arithmetic

div_reg[4]_carry_eqn = A1L58;
div_reg[4]_lut_out = div_reg[4] $ (!div_reg[4]_carry_eqn);
div_reg[4] = DFFEAS(div_reg[4]_lut_out, clk, VCC, , , , , A1L29, );

--A1L78 is div_reg[4]~358
--operation mode is arithmetic

A1L78 = CARRY(div_reg[4] & (!A1L58));


--div_reg[5] is div_reg[5]
--operation mode is arithmetic

div_reg[5]_carry_eqn = A1L78;
div_reg[5]_lut_out = div_reg[5] $ (div_reg[5]_carry_eqn);
div_reg[5] = DFFEAS(div_reg[5]_lut_out, clk, VCC, , , , , A1L29, );

--A1L98 is div_reg[5]~362
--operation mode is arithmetic

A1L98 = CARRY(!A1L78 # !div_reg[5]);


--div_reg[6] is div_reg[6]
--operation mode is arithmetic

div_reg[6]_carry_eqn = A1L98;
div_reg[6]_lut_out = div_reg[6] $ (!div_reg[6]_carry_eqn);
div_reg[6] = DFFEAS(div_reg[6]_lut_out, clk, VCC, , , , , A1L29, );

--A1L19 is div_reg[6]~366
--operation mode is arithmetic

A1L19 = CARRY(div_reg[6] & (!A1L98));


--div_reg[7] is div_reg[7]
--operation mode is arithmetic

div_reg[7]_carry_eqn = A1L19;
div_reg[7]_lut_out = div_reg[7] $ (div_reg[7]_carry_eqn);
div_reg[7] = DFFEAS(div_reg[7]_lut_out, clk, VCC, , , , , A1L29, );

--A1L49 is div_reg[7]~370
--operation mode is arithmetic

A1L49 = CARRY(!A1L19 # !div_reg[7]);


--A1L331 is reduce_nor~320
--operation mode is normal

A1L331 = div_reg[4] # div_reg[5] # div_reg[6] # div_reg[7];


--div_reg[9] is div_reg[9]
--operation mode is arithmetic

div_reg[9]_carry_eqn = A1L69;
div_reg[9]_lut_out = div_reg[9] $ (div_reg[9]_carry_eqn);
div_reg[9] = DFFEAS(div_reg[9]_lut_out, clk, VCC, , , , , A1L29, );

--A1L89 is div_reg[9]~374
--operation mode is arithmetic

A1L89 = CARRY(!A1L69 # !div_reg[9]);


--div_reg[10] is div_reg[10]
--operation mode is arithmetic

div_reg[10]_carry_eqn = A1L89;
div_reg[10]_lut_out = div_reg[10] $ (!div_reg[10]_carry_eqn);
div_reg[10] = DFFEAS(div_reg[10]_lut_out, clk, VCC, , , , , A1L29, );

--A1L001 is div_reg[10]~378
--operation mode is arithmetic

A1L001 = CARRY(div_reg[10] & (!A1L89));


--div_reg[11] is div_reg[11]
--operation mode is arithmetic

div_reg[11]_carry_eqn = A1L001;
div_reg[11]_lut_out = div_reg[11] $ (div_reg[11]_carry_eqn);
div_reg[11] = DFFEAS(div_reg[11]_lut_out, clk, VCC, , , , , A1L29, );

--A1L201 is div_reg[11]~382
--operation mode is arithmetic

A1L201 = CARRY(!A1L001 # !div_reg[11]);


--div_reg[8] is div_reg[8]
--operation mode is arithmetic

div_reg[8]_carry_eqn = A1L49;
div_reg[8]_lut_out = div_reg[8] $ (!div_reg[8]_carry_eqn);
div_reg[8] = DFFEAS(div_reg[8]_lut_out, clk, VCC, , , , , A1L29, );

--A1L69 is div_reg[8]~386
--operation mode is arithmetic

A1L69 = CARRY(div_reg[8] & (!A1L49));


--A1L431 is reduce_nor~321
--operation mode is normal

A1L431 = div_reg[9] # div_reg[10] # div_reg[11] # !div_reg[8];


--div_reg[12] is div_reg[12]
--operation mode is arithmetic

div_reg[12]_carry_eqn = A1L201;
div_reg[12]_lut_out = div_reg[12] $ (!div_reg[12]_carry_eqn);
div_reg[12] = DFFEAS(div_reg[12]_lut_out, clk, VCC, , , , , A1L29, );

--A1L401 is div_reg[12]~390
--operation mode is arithmetic

A1L401 = CARRY(div_reg[12] & (!A1L201));


--div_reg[13] is div_reg[13]
--operation mode is arithmetic

div_reg[13]_carry_eqn = A1L401;
div_reg[13]_lut_out = div_reg[13] $ (div_reg[13]_carry_eqn);
div_reg[13] = DFFEAS(div_reg[13]_lut_out, clk, VCC, , , , , A1L29, );

--A1L601 is div_reg[13]~394
--operation mode is arithmetic

A1L601 = CARRY(!A1L401 # !div_reg[13]);


--div_reg[14] is div_reg[14]
--operation mode is arithmetic

div_reg[14]_carry_eqn = A1L601;
div_reg[14]_lut_out = div_reg[14] $ (!div_reg[14]_carry_eqn);
div_reg[14] = DFFEAS(div_reg[14]_lut_out, clk, VCC, , , , , A1L29, );

--A1L801 is div_reg[14]~398
--operation mode is arithmetic

A1L801 = CARRY(div_reg[14] & (!A1L601));


--div_reg[15] is div_reg[15]
--operation mode is normal

div_reg[15]_carry_eqn = A1L801;
div_reg[15]_lut_out = div_reg[15] $ (div_reg[15]_carry_eqn);
div_reg[15] = DFFEAS(div_reg[15]_lut_out, clk, VCC, , , , , A1L29, );


--A1L531 is reduce_nor~322
--operation mode is normal

A1L531 = div_reg[12] # div_reg[13] # div_reg[14] # div_reg[15];


--A1L631 is reduce_nor~323
--operation mode is normal

A1L631 = A1L231 # A1L331 # A1L431 # A1L531;


--A1L121 is key_entry2~90
--operation mode is normal

A1L121 = !A1L6 # !send_state[1] # !send_state[2] # !send_state[0];


--rxd_reg1 is rxd_reg1
--operation mode is normal

rxd_reg1_lut_out = rxd;
rxd_reg1 = DFFEAS(rxd_reg1_lut_out, clkbaud8x, rst, , , , , , );


--recstart is recstart
--operation mode is normal

recstart_lut_out = A1L031;
recstart = DFFEAS(recstart_lut_out, clkbaud8x, rst, , A1L821, , , , );


--A1L07 is div8_rec_reg[2]~51
--operation mode is normal

A1L07 = div8_rec_reg[1] & div8_rec_reg[0] & recstart;


--A1L86 is div8_rec_reg[1]~52
--operation mode is normal

A1L86 = div8_rec_reg[0] & recstart;


--A1L212 is state_rec[0]~802
--operation mode is normal

A1L212 = state_rec[3] & (state_rec[2] # state_rec[1]) # !state_rec[3] & !state_rec[2] & !state_rec[1] & !state_rec[0];


--A1L031 is reduce_nor~5
--operation mode is normal

A1L031 = !state_rec[3] & !state_rec[0] & !state_rec[2] & !state_rec[1];


--recstart_tmp is recstart_tmp
--operation mode is normal

recstart_tmp_lut_out = rxd_reg2 & (!recstart_tmp & !rxd_reg1);
recstart_tmp = DFFEAS(recstart_tmp_lut_out, clkbaud8x, rst, , A1L031, , , , );


--A1L312 is state_rec[0]~803
--operation mode is normal

A1L312 = A1L031 & (!recstart_tmp) # !A1L031 & (A1L212 # !A1L881);


--A1L61 is add~1063
--operation mode is normal

A1L61 = state_rec[0] & state_rec[1];


--A1L712 is state_rec~804
--operation mode is normal

A1L712 = state_rec[3] & (state_rec[0] # state_rec[2] # state_rec[1]);


--A1L71 is add~1064
--operation mode is normal

A1L71 = state_rec[0] & state_rec[2] & state_rec[1];


--A1L142 is txd_buf~1758
--operation mode is normal

A1L142 = send_state[1] & state_tras[1] & (!send_state[2]);


--txd_buf[2] is txd_buf[2]
--operation mode is normal

txd_buf[2]_lut_out = A1L342 # txd_buf[3] & !state_tras[3] # !key_entry2;
txd_buf[2] = DFFEAS(txd_buf[2]_lut_out, clkbaud8x, rst, , A1L332, , , , );


--A1L832 is txd_buf[6]~1759
--operation mode is normal

A1L832 = !state_tras[1] & (state_tras[2] # !state_tras[0]) # !state_tras[3];


--cnt_delay[8] is cnt_delay[8]
--operation mode is arithmetic

cnt_delay[8]_carry_eqn = A1L93;
cnt_delay[8]_lut_out = cnt_delay[8] $ (!cnt_delay[8]_carry_eqn);
cnt_delay[8] = DFFEAS(cnt_delay[8]_lut_out, clk, VCC, , A1L15, , , A1L05, );

--A1L14 is cnt_delay[8]~605
--operation mode is arithmetic

A1L14 = CARRY(cnt_delay[8] & (!A1L93));


--cnt_delay[10] is cnt_delay[10]
--operation mode is arithmetic

cnt_delay[10]_carry_eqn = A1L34;
cnt_delay[10]_lut_out = cnt_delay[10] $ (!cnt_delay[10]_carry_eqn);
cnt_delay[10] = DFFEAS(cnt_delay[10]_lut_out, clk, VCC, , A1L15, , , A1L05, );

--A1L54 is cnt_delay[10]~609
--operation mode is arithmetic

A1L54 = CARRY(cnt_delay[10] & (!A1L34));


--cnt_delay[12] is cnt_delay[12]
--operation mode is arithmetic

cnt_delay[12]_carry_eqn = A1L74;
cnt_delay[12]_lut_out = cnt_delay[12] $ (!cnt_delay[12]_carry_eqn);
cnt_delay[12] = DFFEAS(cnt_delay[12]_lut_out, clk, VCC, , A1L15, , , A1L05, );

--A1L94 is cnt_delay[12]~613
--operation mode is arithmetic

A1L94 = CARRY(cnt_delay[12] & (!A1L74));


--cnt_delay[13] is cnt_delay[13]
--operation mode is arithmetic

cnt_delay[13]_carry_eqn = A1L94;
cnt_delay[13]_lut_out = cnt_delay[13] $ (cnt_delay[13]_carry_eqn);
cnt_delay[13] = DFFEAS(cnt_delay[13]_lut_out, clk, VCC, , A1L15, , , A1L05, );

--A1L35 is cnt_delay[13]~617
--operation mode is arithmetic

A1L35 = CARRY(!A1L94 # !cnt_delay[13]);


--A1L731 is reduce_nor~324
--operation mode is normal

A1L731 = !cnt_delay[13] # !cnt_delay[12] # !cnt_delay[10] # !cnt_delay[8];


--cnt_delay[18] is cnt_delay[18]
--operation mode is arithmetic

cnt_delay[18]_carry_eqn = A1L16;
cnt_delay[18]_lut_out = cnt_delay[18] $ (!cnt_delay[18]_carry_eqn);
cnt_delay[18] = DFFEAS(cnt_delay[18]_lut_out, clk, VCC, , A1L15, , , A1L05, );

--A1L36 is cnt_delay[18]~621
--operation mode is arithmetic

A1L36 = CARRY(cnt_delay[18] & (!A1L16));


--cnt_delay[19] is cnt_delay[19]