?? ppg.asm.rpt
字號:
Assembler report for ppg
Tue Oct 14 14:38:09 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.sof
6. Assembler Device Options: G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.pof
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Oct 14 14:38:09 2008 ;
; Revision Name ; ppg ;
; Top-level Entity Name ; ppg ;
; Family ; Cyclone II ;
; Device ; EP2C20F484C7 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; Off ; Off ;
; Use configuration device ; On ; On ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+-------------------------------------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------------------------------------+
; File Name ;
+-------------------------------------------------------------------------+
; G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.sof ;
; G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.pof ;
+-------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Assembler Device Options: G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.sof ;
+----------------+----------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------------------------------+
; Device ; EP2C20F484C7 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x001B4C8C ;
+----------------+----------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Assembler Device Options: G:/EEC 587 Rapid Digital System Prototyping/VHDL/ppg(real ab5 )/ppg.pof ;
+--------------------+------------------------------------------------------------------------------+
; Option ; Setting ;
+--------------------+------------------------------------------------------------------------------+
; Device ; EPCS16 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x1DD98355 ;
; Compression Ratio ; 3 ;
+--------------------+------------------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
Info: Processing started: Tue Oct 14 14:38:03 2008
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ppg -c ppg
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 177 megabytes
Info: Processing ended: Tue Oct 14 14:38:10 2008
Info: Elapsed time: 00:00:07
Info: Total CPU time (on all processors): 00:00:04
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