library ieee;
use ieee.std_logic_1164.all;
entity lab7 is
port(
        clk1: in std_logic;
  ssega,ssegb,ssegc,ssegd:out std_logic_vector(6 downto 0)
);
end lab7;

architecture one of lab7 is
COMPONENT bin2led0 
  port(
      bin0: in std_logic_vector(3 downto 0);
      sseg0: out std_logic_vector(6 downto 0)
   );

end COMPONENT;

COMPONENT bin2led1 
  port(
      bin1: in std_logic_vector(3 downto 0);
      sseg1: out std_logic_vector(6 downto 0)
   );

end COMPONENT;
COMPONENT bin2led2 
  port(
      bin2: in std_logic_vector(3 downto 0);
      sseg2: out std_logic_vector(6 downto 0)
   );

end COMPONENT;
COMPONENT bin2led3 
  port(
      bin3: in std_logic_vector(3 downto 0);
      sseg3: out std_logic_vector(6 downto 0)
   );

end COMPONENT;


COMPONENT heartbeat
port(
     clk:in std_logic;
     d0,d1,d2,d3:out std_logic_vector(3 downto 0)
);
end COMPONENT;

signal a,b,c,d:std_logic_vector(3 downto 0);
begin
u1: heartbeat port map(clk=>clk1,d0=>a,d1=>b,d2=>c,d3=>d);
u2: bin2led0 port map(bin0=>a,sseg0=>ssega);
u3: bin2led1 port map(bin1=>b,sseg1=>ssegb);
u4: bin2led2 port map(bin2=>c,sseg2=>ssegc);
u5: bin2led3 port map(bin3=>d,sseg3=>ssegd);


end one;