library ieee;
use ieee.std_logic_1164.all;
entity lab4 is
port(
              rin :in std_logic_vector(10 downto 1); 
     sseg1,sseg2:out std_logic_vector(6 downto 0)
);
end lab4;

architecture one of lab4 is
COMPONENT bin2led 
  port(
      bin: in std_logic_vector(3 downto 0);
      sseg: out std_logic_vector(6 downto 0)
   );
end COMPONENT;

COMPONENT enconder 
  port( 
      r:in std_logic_vector(10 downto 1); 
      fst, snd:out std_logic_vector(3 downto 0)
);
end COMPONENT;

signal a,b: std_logic_vector(3 downto 0);
begin
u1: enconder port map(r=>rin, fst=>a, snd=>b);
u2: bin2led port map(bin=>a, sseg=>sseg1);
u3: bin2led port map(bin=>b, sseg=>sseg2);
end one;