?? lab4.vwf

?? 用VHDL編譯的源代碼
?? VWF
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上一頁 12
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 40.0;
		LEVEL 0 FOR 20.0;
	}
}

TRANSITION_LIST("rin[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 90.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 60.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
	}
}

TRANSITION_LIST("rin[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 40.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 30.0;
	}
}

TRANSITION_LIST("rin[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 80.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 40.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 50.0;
	}
}

TRANSITION_LIST("rin[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 80.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
	}
}

TRANSITION_LIST("sseg1[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg1[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg1[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg1[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg1[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg1[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg1[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg2[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg2[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg2[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg2[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg2[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg2[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("sseg2[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "rin";
	EXPAND_STATUS = EXPANDED;
	RADIX = ASCII;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
	CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10;
}

DISPLAY_LINE
{
	CHANNEL = "rin[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 1;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rin[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rin[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rin[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rin[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rin[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rin[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rin[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rin[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "rin[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "sseg1";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 11;
	TREE_LEVEL = 0;
	CHILDREN = 12, 13, 14, 15, 16, 17, 18;
}

DISPLAY_LINE
{
	CHANNEL = "sseg1[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "sseg1[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "sseg1[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "sseg1[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "sseg1[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "sseg1[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "sseg1[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 11;
}

DISPLAY_LINE
{
	CHANNEL = "sseg2";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 19;
	TREE_LEVEL = 0;
	CHILDREN = 20, 21, 22, 23, 24, 25, 26;
}

DISPLAY_LINE
{
	CHANNEL = "sseg2[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 19;
}

DISPLAY_LINE
{
	CHANNEL = "sseg2[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 19;
}

DISPLAY_LINE
{
	CHANNEL = "sseg2[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 19;
}

DISPLAY_LINE
{
	CHANNEL = "sseg2[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 23;
	TREE_LEVEL = 1;
	PARENT = 19;
}

DISPLAY_LINE
{
	CHANNEL = "sseg2[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 19;
}

DISPLAY_LINE
{
	CHANNEL = "sseg2[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 19;
}

DISPLAY_LINE
{
	CHANNEL = "sseg2[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 19;
}

TIME_BAR
{
	TIME = 13850;
	MASTER = TRUE;
}
;
上一頁 12
?? 文件大小 352 K
?? 上傳用戶 lyyfengyutongzh
?? 所屬分類 VHDL/FPGA/Verilog
??? 相關標簽

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?? lab4.vwf

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