--實驗11 組合邏輯控制器實驗(頭文件)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

PACKAGE cpu_defs IS
	TYPE     opcode IS (load, store, add, sub, bne);	
	CONSTANT word_w: NATURAL :=8;
	CONSTANT op_w: NATURAL :=3;
	CONSTANT rfill: STD_LOGIC_VECTOR(op_w-1 downto 0):=(others =>'0');
	--FUNCTIOn slv2op(slv:IN STD_LOGIC_VECTOR) RETURN opcode;
	FUNCTION op2slv(op:in opcode) RETURN STD_LOGIC_VECTOR;
END PACKAGE cpu_defs;

PACKAGE BODY cpu_defs IS
	TYPE     optable IS ARRAY(opcode) OF STD_LOGIC_VECTOR(op_w-1 DOWNTO 0);
	CONSTANT trans_table:optable :=("000", "001", "010", "011", "100");
	FUNCTION op2slv(op:IN opcode) RETURN STD_LOGIC_VECTOR IS
	BEGIN
			RETURN trans_table(op);
	END FUNCTION op2slv;
	--function slv2op(slv:in std_logic_vector) return opcode is
	--	variable transop:opcode;
	--	begin
	--		for i in opcode loop
	--			if slv=trans_table(i) then
	--				transop:=i;
	--			end if;
	--		end loop;
	--		return transop;
	--end function slv2op;
END PACKAGE BODY cpu_defs;