?? freedev_cycloneii_50.map.rpt
字號:
; |payload_buffer_s1_arbitrator:the_payload_buffer_s1| ; 43 (43) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|freedev_cycloneII_50:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1 ;
; |sysid_control_slave_arbitrator:the_sysid_control_slave| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|freedev_cycloneII_50:inst|sysid_control_slave_arbitrator:the_sysid_control_slave ;
; |tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave| ; 69 (69) ; 76 (76) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave ;
; |sld_hub:sld_hub_inst| ; 76 (33) ; 60 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst ;
; |lpm_decode:instruction_decoder| ; 5 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder ;
; |decode_rpe:auto_generated| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated ;
; |lpm_shiftreg:jtag_ir_register| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register ;
; |sld_dffex:BROADCAST| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst|sld_dffex:BROADCAST ;
; |sld_dffex:IRF_ENA_0| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0 ;
; |sld_dffex:IRF_ENA| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA ;
; |sld_dffex:IRSR| ; 1 (1) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst|sld_dffex:IRSR ;
; |sld_dffex:RESET| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst|sld_dffex:RESET ;
; |sld_dffex:\GEN_IRF:1:IRF| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF ;
; |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF ;
; |sld_jtag_state_machine:jtag_state_machine| ; 20 (20) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ;
; |sld_rom_sr:HUB_INFO_REG| ; 16 (16) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |freedev_cycloneII_50_top|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ;
+--------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+--------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+--------------------+
; freedev_cycloneII_50:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; rf_ram.mif ;
; freedev_cycloneII_50:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_ca01:auto_generated|ALTSYNCRAM ; M4K ; Single Port ; 256 ; 32 ; -- ; -- ; 8192 ; data_RAM.hex ;
; freedev_cycloneII_50:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_gq01:auto_generated|ALTSYNCRAM ; M4K ; Single Port ; 896 ; 32 ; -- ; -- ; 28672 ; firmware_ROM.hex ;
; freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ;
; freedev_cycloneII_50:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram|altsyncram_toc1:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ;
; freedev_cycloneII_50:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|ALTSYNCRAM ; M4K ; Single Port ; 8192 ; 16 ; -- ; -- ; 131072 ; payload_buffer.hex ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+--------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by SYN_PRESERVE, DONT_TOUCH ;
+-------------------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------+
; Register Name ; Protected by SYN_PRESERVE ; Not to be Touched by Netlist Optimizations ;
+-------------------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------+
; freedev_cycloneII_50:inst|freedev_cycloneII_50_reset_clk_domain_synch_module:freedev_cycloneII_50_reset_clk_domain_synch|data_out ; yes ; yes ;
; freedev_cycloneII_50:inst|freedev_cycloneII_50_reset_clk_domain_synch_module:freedev_cycloneII_50_reset_clk_domain_synch|data_in_d1 ; yes ; yes ;
+-------------------------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 768 ;
; Number of registers using Synchronous Clear ; 84 ;
; Number of registers using Synchronous Load ; 179 ;
; Number of registers using Asynchronous Clear ; 705 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 344 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register ; Fan out ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|select_n_to_the_cfi_flash_0 ; 1 ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn ; 1 ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash_0 ; 1 ;
; freedev_cycloneII_50:inst|cpu_0:the_cpu_0|i_read ; 23 ;
; freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0] ; 5 ;
; sld_hub:sld_hub_inst|hub_tdo ?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -