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--W1_select_n_to_the_cfi_flash_0 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|select_n_to_the_cfi_flash_0
W1_select_n_to_the_cfi_flash_0 = DFFEAS(W1L67, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_readn is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn
W1_tri_state_bridge_0_readn = DFFEAS(W1L101, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_write_n_to_the_cfi_flash_0 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash_0
W1_write_n_to_the_cfi_flash_0 = DFFEAS(W1L301, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[24] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[24]
W1_tri_state_bridge_0_address[24] = DFFEAS(W1L001, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[23] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[23]
W1_tri_state_bridge_0_address[23] = DFFEAS(W1L99, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[22] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[22]
W1_tri_state_bridge_0_address[22] = DFFEAS(W1L89, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[21] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[21]
W1_tri_state_bridge_0_address[21] = DFFEAS(W1L79, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[20] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[20]
W1_tri_state_bridge_0_address[20] = DFFEAS(W1L69, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[19] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[19]
W1_tri_state_bridge_0_address[19] = DFFEAS(W1L59, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[18] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[18]
W1_tri_state_bridge_0_address[18] = DFFEAS(W1L49, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[17] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[17]
W1_tri_state_bridge_0_address[17] = DFFEAS(W1L39, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[16] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[16]
W1_tri_state_bridge_0_address[16] = DFFEAS(W1L29, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[15] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[15]
W1_tri_state_bridge_0_address[15] = DFFEAS(W1L19, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[14] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[14]
W1_tri_state_bridge_0_address[14] = DFFEAS(W1L09, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[13] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[13]
W1_tri_state_bridge_0_address[13] = DFFEAS(W1L98, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[12] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[12]
W1_tri_state_bridge_0_address[12] = DFFEAS(W1L88, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[11] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[11]
W1_tri_state_bridge_0_address[11] = DFFEAS(W1L78, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[10] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[10]
W1_tri_state_bridge_0_address[10] = DFFEAS(W1L68, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[9] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[9]
W1_tri_state_bridge_0_address[9] = DFFEAS(W1L58, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[8] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[8]
W1_tri_state_bridge_0_address[8] = DFFEAS(W1L48, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[7] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[7]
W1_tri_state_bridge_0_address[7] = DFFEAS(W1L38, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[6] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[6]
W1_tri_state_bridge_0_address[6] = DFFEAS(W1L28, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[5] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[5]
W1_tri_state_bridge_0_address[5] = DFFEAS(W1L18, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[4] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[4]
W1_tri_state_bridge_0_address[4] = DFFEAS(W1L08, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[3] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[3]
W1_tri_state_bridge_0_address[3] = DFFEAS(W1L97, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[2] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[2]
W1_tri_state_bridge_0_address[2] = DFFEAS(W1L87, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[1] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[1]
W1_tri_state_bridge_0_address[1] = DFFEAS(W1L77, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--A1L23 is altera_internal_jtag~TDO
A1L23 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L51);

--A1L33 is altera_internal_jtag~TMSUTAP
A1L33 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L51);

--A1L13 is altera_internal_jtag~TCKUTAP
A1L13 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L51);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L51);


--W1_tri_state_bridge_0_avalon_slave_arb_addend[1] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1]
W1_tri_state_bridge_0_avalon_slave_arb_addend[1] = DFFEAS(W1L731, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--H1_F_pc[25] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|F_pc[25]
H1_F_pc[25] = AMPP_FUNCTION(CLK, H1L016, H1L669, E1_data_out, H1L616, H1L516, H1_W_valid);


--H1_i_read is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|i_read
H1_i_read = AMPP_FUNCTION(CLK, H1_i_read_nxt, E1_data_out);


--W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1]
W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEAS(W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0], CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0]
W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEAS(W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1L72 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~57
W1L72 = H1_F_pc[25] & !H1_i_read & !W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & !W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0];


--W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_slavearbiterlockenable
W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable = DFFEAS(W1L151, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1
W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 = DFFEAS(W1L37, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--H1_W_alu_result[27] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|W_alu_result[27]
H1_W_alu_result[27] = AMPP_FUNCTION(CLK, H1L667, H1_E_shift_rot_result[27], E1_data_out, H1L921, H1_R_ctrl_shift_rot);


--H1_d_read is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|d_read
H1_d_read = AMPP_FUNCTION(CLK, H1_d_read_nxt, E1_data_out);


--AB1_d_write is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|d_write
AB1_d_write = AMPP_FUNCTION(CLK, H1_d_write_nxt, E1_data_out);


--W1_cpu_0_data_master_requests_cfi_flash_0_s1 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1
W1_cpu_0_data_master_requests_cfi_flash_0_s1 = H1_W_alu_result[27] & (H1_d_read # AB1_d_write);


--W1L82 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~58
W1L82 = W1L72 & (!W1_cpu_0_data_master_requests_cfi_flash_0_s1 # !W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 # !W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable);


--W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1
W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 = DFFEAS(W1L57, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1L71 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~144
W1L71 = H1_i_read # !W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 # !H1_F_pc[25] # !W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable;


--W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1]
W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEAS(W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0], CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0]
W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEAS(W1L52, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1L81 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~145
W1L81 = W1_cpu_0_data_master_requests_cfi_flash_0_s1 & (!W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & !W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] # !H1_d_read);


--H1_d_byteenable[3] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|d_byteenable[3]
H1_d_byteenable[3] = AMPP_FUNCTION(CLK, H1L691, E1_data_out);


--H1_d_byteenable[1] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|d_byteenable[1]
H1_d_byteenable[1] = AMPP_FUNCTION(CLK, H1L491, E1_data_out);


--J1_cpu_0_data_master_dbs_address[1] is freedev_cycloneII_50:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1]
J1_cpu_0_data_master_dbs_address[1] = DFFEAS(J1L5, CLK, !E1_data_out,  , J1L4,  ,  ,  ,  );


--W1L61 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1[1]~46
W1L61 = J1_cpu_0_data_master_dbs_address[1] & H1_d_byteenable[3] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_byteenable[1]);


--H1_d_byteenable[2] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|d_byteenable[2]
H1_d_byteenable[2] = AMPP_FUNCTION(CLK, H1L591, E1_data_out);


--H1_d_byteenable[0] is freedev_cycloneII_50:inst|cpu_0:the_cpu_0|d_byteenable[0]
H1_d_byteenable[0] = AMPP_FUNCTION(CLK, H1L791, E1_data_out);


--W1L51 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1[0]~47
W1L51 = J1_cpu_0_data_master_dbs_address[1] & H1_d_byteenable[2] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_byteenable[0]);


--J1_cpu_0_data_master_no_byte_enables_and_last_term is freedev_cycloneII_50:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_no_byte_enables_and_last_term
J1_cpu_0_data_master_no_byte_enables_and_last_term = DFFEAS(J1L631, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1L91 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~146
W1L91 = !J1_cpu_0_data_master_no_byte_enables_and_last_term & (W1L61 # W1L51);


--W1L02 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~147
W1L02 = W1L71 & W1L81 & (W1L91 # !AB1_d_write);


--W1_tri_state_bridge_0_avalon_slave_arb_addend[0] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0]
W1_tri_state_bridge_0_avalon_slave_arb_addend[0] = DFFEAS(W1L431, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1L67 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_select_n_to_the_cfi_flash_0~0
W1L67 = W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & (W1L82 # W1L02) # !W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !W1_tri_state_bridge_0_avalon_slave_arb_addend[0] & (W1L82 # W1L02);


--E1_data_out is freedev_cycloneII_50:inst|freedev_cycloneII_50_reset_clk_domain_synch_module:freedev_cycloneII_50_reset_clk_domain_synch|data_out
E1_data_out = DFFEAS(E1_data_in_d1, CLK, C1_inst4,  ,  ,  ,  ,  ,  );


--W1L541 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[0]~58
W1L541 = W1L82 & (W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !W1L02 # !W1_tri_state_bridge_0_avalon_slave_arb_addend[0]);


--W1L641 is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~59
W1L641 = W1L02 & (W1_tri_state_bridge_0_avalon_slave_arb_addend[1] # !W1L82 & !W1_tri_state_bridge_0_avalon_slave_arb_addend[0]);


--W1_cfi_flash_0_s1_in_a_read_cycle is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_in_a_read_cycle
W1_cfi_flash_0_s1_in_a_read_cycle = W1L541 # H1_d_read & W1L641;


--W1_cfi_flash_0_s1_wait_counter[3] is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[3]
W1_cfi_flash_0_s1_wait_counter[3] = DFFEAS(W1L7, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );


--W1_d1_reasons_to_wait is freedev_cycloneII_50:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_reasons_to_wait
W1_d1_reasons_to_wait = DFFEAS(W1L341, CLK, !E1_data_out,  ,  ,  ,  ,  ,  );